ITB clock lines -- clk share between blocks : How ?

[Altera_Forum]

Hi  

 On Stratix IV GX230 board, I would like to use REFCLK_R5 (pins: G1, G2, on transceiver block BankQR2) to drive REFCLK_R1 (pins: AL1, AL2, on transceiver block BandQR0). Stratix IV handbook seems to suggest that this is feasible. On vol 2, section I, chapter 2, p.g. 2-1~8. Especially on p.g. 2-8, ITB section.  We do not know how to do this on Quartus version 11.1. Could anyone help shed a light ?  Thanks

[Altera_Forum]

Hello, 

 You want the reference clock that feeds the REFCLK_R5 input to be shared by the QR0 and QR2 GXB blocks ?   Indeed, it is feasible as long as the GXB blocks are located on the same side of the device. As ITB lines are internal clock paths, you don't have to route any external trace on your PCB. The connection is done by the Quartus fitter, this is just a matter of gateware writing.   If you are instantiating GXB RX-Only blocks, you simply have to tie together their "rx_cruclk" inputs together and to connect them to your reference clock input pin.   If you are instantiating GXB TX&RX blocks, you can either use the "rx_cruclk" inputs as previously or use their "pll_inclk" inputs depending on which parts of the transceivers you want to synchronize.

[Altera_Forum]

Thanks genoli ! 

It is very helpful.   Though we meet another problem now. Before we can use Quartus fitter, the project has to be analysis&synthesis , where we meet analysis&synthesis error,  "Error (10650): Verilog HDL Display System Task at altpll_0.v(213): The width_clock of 7 specified is not supported in STRATIXIV Error (12152): Can't elaborate user hierarchy "jesdcon_a:u_jesdcon_a|altpll_0:the_altpll_0" " -- but this is totally another problem.