Stratix IV, compile error, CLK error, PLL error

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Stratix IV, compile error, CLK error, PLL error

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When we analysis&synthesis (or compile), we meet

"Error (10650): Verilog HDL Display System Task at altpll_0.v(213): The width_clock of 7 specified is not supported in STRATIXIV

Error (12152): Can't elaborate user hierarchy "jesdcon_a:u_jesdcon_a|altpll_0:the_altpll_0"

Actually on STRATIX IV there are 10 clocks, but the 1st error complains about 7 clocks.

The project was formerly designed for Altera Aria II (which has 7 clocks), and now we are transferring the project onto Stratix IV. Probably this is the reason, but we do not know how to solve the errors. The Quartus version we are using is 11.1.

Device type has been set as "Stratix IV" on Quartus, on Qsys and on the Qys PLL module.

Could anyone help shed a light ?

Thanks

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