Provided that the Nios II is to be run from off chip memory due to the program being too big, this could e.g be an SRAM or SDRAM or even Flash. How would one download the program into these memories in the first place?
Is it going to something like
1.FPGA configures itself from design 1, this design copies Nios II program into the external memory from the configuration memory device or directly from JTAG. Then the FPGA configures itself with the actual Design 2 containing Nios II or
2. FPGA configures itself with design 1, this design shall copy program from configuration memory or JTAG into external memory and then change its instruction master and reset and exception vectors to external memory's addresses.
3. Something else.
