HiI have been try top simulate my design using modelsim. I get no warnings when the simulation starts but after a while I see the following in my terminal: Fatal: (vsim-4) ****** Memory allocation failure. ***** Attempting to allocate 131072 bytes Please check your system for available memory and swap space. ** Fatal: vsimk is exiting with code 9. I understand that it might be because the design is pretty big. But is there a way to circumvent this and simulate my design? How do I proceed? :(:( I really need the simulation to complete my project. Kindly respond Thanks sudheera
I am running it on modelsim ase. I do the analysis and synthesis of the RTL design (verilog HDL) on Quartus Prime software. Hope this answers the question.
Not even close. Let's try this again:What operating system are you using? Windows XP, 7, 8, or 10? 32bit or 64bit? Or version of Linux (use 'uname -a')? What hardware platform are you using? I'm guessing an Intel PC, but how much physical memory does it have? What version of Quartus are you using? What version of ModelSim?
It means your machine does not have enough ram (and virtual ram) to complete the simulation.Do you have some large arrays in the design? Are you modelling DDR or something?