Implementing OpenCL in an existing SoC project

[Altera_Forum]

Hi 

 I have an existing Cyclone V project, with the HPS and custom IP-cores instantiated in QSys (board.qsys). Additionally I have custom modules in VHDL, so I have something like:  -top.vhd -- module 1 -----module 1.1 -----module 1.2 -- module 2 -- board.qsys  I have modified the board.qsys file using the c5soc reference platform. As I understand I have to include this in the system.qsys, which in turn is included in the top.v file of the OpenCL project:  -top.v --system.qsys ----board.qsys  Additionally I have to compile the board.qsys project to ensure timing and export the result to a .qpf file. But I'm not sure where the custom VHDL modules goes: Do they have to be part of the exported .qpf file, do I have to wrap them in an IP-core and include it in the board.qsys file or so I have to remap it in my new top.v file where system.qsys is included?  Thank you for your time, it is much appreciated! Nikolai

[Altera_Forum]

The custom platform guide mentions that you have to "preserve all non kernel logic": https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/opencl-sdk/ug_aocl_custom_platform_toolkit.pdf 

At the same time, non of the reference platforms that was included in my Cyclone V OpenCL download, have VHDL modules below top.v(hd)