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Honored Contributor I

Implementing OpenCL in an existing SoC project



I have an existing Cyclone V project, with the HPS and custom IP-cores instantiated in QSys (board.qsys). 

Additionally I have custom modules in VHDL, so I have something like: 



-- module 1 

-----module 1.1 

-----module 1.2 

-- module 2 

-- board.qsys 


I have modified the board.qsys file using the c5soc reference platform. 

As I understand I have to include this in the system.qsys, which in turn is included in the top.v file of the OpenCL project: 






Additionally I have to compile the board.qsys project to ensure timing and export the result to a .qpf file. 

But I'm not sure where the custom VHDL modules goes: 

Do they have to be part of the exported .qpf file, do I have to wrap them in an IP-core and include it in the board.qsys file or so I have to remap it in my new top.v file where system.qsys is included? 


Thank you for your time, it is much appreciated! 

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Honored Contributor I

The custom platform guide mentions that you have to "preserve all non kernel logic": 

At the same time, non of the reference platforms that was included in my Cyclone V OpenCL download, have VHDL modules below top.v(hd)