Here is my problem :
I have a package which is written in VHDL.
I would like to import it in my SystemVerilog design.
In Modelsim, I would simply compile the VHDL file with a special flag so it's compatible
=> vcom -mixedsvvh package.vhd
and then import it in my SystemVerilog file with
=> import package::*;
And everything works fine during the simulation.
In Quartus, I can't find any way to make the VHDL package compatible with my SV design.
When I try to compile in Quartus, I get the following error :
Error (10161): Verilog HDL error at SystemVerilogDesign.sv(4): object "package" is not declared. Verify the object name is correct. If the name is correct, declare the object.
It is exactly the same problem as described in this link from 3 years ago :
Thank you for any information that could help !
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