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Importing & Exporting a Post-Synthesis Netlist

Honored Contributor II



I'm looking at migrating a design that I've already implemented on Xilinx FPGAs that is a simple TMR'ed application. On the Xilinx FPGA I TMR'ed my verilog design via modifcation to the post-synthesis netlist which was then re-imported back into Vivado; with it working successfully. 


How do I go about doing this on Intel/Altera FPGAs? I'm having difficulties with both exporting and importing the netlist as it expects qpf files which are binary files. 


Any ideas - even if it's via TCL scripts? 


Thanks Sam
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