Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15469 Discussions

When to disable burst interleaving?

Altera_Forum
Honored Contributor II
845 Views

Hello, 

 

Can someone please explain under what conditions to disable burst interleaving on the DDR memory? I've read the Programming Guide and Best Practices but it's not entirely clear. 

 

Here's some example situations: 

1.) Kernel reads data and generates an output; the read and write data rates are identical.  

2.) Kernel reads data and generates an output; the write data rate is twice as high as the read data rate. 

3.) Same as situation 1, except now I want to simultaneously perform kernel execution, a nonblocking PCIe read, and a nonblocking PCIe write.
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
98 Views

I have tried this a few times for my complex kernels and every time, without exception, it resulted in lower performance. The only case I could achieve higher performance by disabling the burst interleaving and performing manual buffer placement was for the stream benchmark which is a very simple kernel. It is possible that in certain cases, if the read and write rate are equal, you might be able to get higher performance by disabling burst interleaving. However, for cases where the read and write rate are NOT identical, it is probably best to use interleaving since if you don't, the access with higher rate might fully saturate the bandwidth the bank it is assigned to, while the one with lower rate might under-utilize the bandwidth of its own bank, while with interleaving, the total bandwidth will be shared between them. With respect to your 3rd scenario, I don't think the effect of burst interleaving on it will be any different from the first scenario. 

 

At the end of the day, you should probably test this on a case by case basis; there is probably no rule of thumb for when to disable burst interleaving and when to keep it.
Reply