In A10/C10 hard ip for PCIe, size of address pages can't be 128KB to 2MB

[万江]

Hello,

I'm testing PCIe on a C10 devkit by quartus 18.0pro. Application interface type = Avalon_MM(no DMA), Avalon_MM address width = 32bits.

Under Avalon-MM settings tab, why size of address pages can NOT be set to between 17-21bits(128KB-2MB)?

By the way, if Avalon_MM address width = 64bits, and address width of accessible PCIe memory space = 20. When an avalon-mm to PCIe transaction occurs, what are higher 42 address bits on PCIe? All zeroes?

Thanks

[Nathan_R_Intel]

Wanli Jiang, My apologies for the delayed first response. I missed your case and will provide faster response moving forward. Please check my response to your question: Currently, due to address translation algorithm, some size of address pages cannot be set. The address translation replaces the MSB of AVMM address with value from a specific translation table. Only the LSB remains unchanged. Hence, that's why you cannot set to between 17-21 bits. Question: the way, if Avalon_MM address width = 64bits, and address width of accessible PCIe memory space = 20. When an avalon-mm to PCIe transaction occurs, what are higher 42 address bits on PCIe? All zeroes? Answer: Avalon address is interpreted as following for 64 bits: • Bits [31:24] select the TX slave module port from among other slaves connected to the same master by the system interconnect fabric. The decode is based on the base addresses assigned in Platform Designer. • Bits [23:20] select the address translation table entry. • Bits [63:20] of the address translation table entry become PCI Express address bits [63:20]. • Bits [19:0] are passed through and become PCI Express address bits [19:0]. More information related to AVMM to PCIe Address Translation is available in Section A.4.10 (Pg 174) of our user guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf Regards, Nathan

[万江]

Hi Nathan,

Thank you for your explanation

But according to my testing, I feel the Address Translation Table is available only when Avalon_MM address width = 32bits

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When Avalon_MM address width = 32 bits

Under Avalon-MM settings tab, 'Number of address pages' and 'Size of address pages' appear, and 'Address width of accessible PCIe memory space' disappears

If I set Number of address pages = 16 and Size of address pages = 64KBytes(16 bits), from Component Instantiation \ Compilation Info \ Signals & Interfaces, I read the address width of 'txs interface' is 20bits. That is 64KB * 16 = 1MB.

On qsys side:

address[15:0] are passed through and become PCIe address[15:0]

address[19:16] select one from the 16 address translation table entries

address[31:20] are determined by Assign Base Addresses

On PCIe side:

address[15:0] are identical with qsys address[15:0]

address[31:16]/address[63:16] come from the selected address translation table entry, b[1:0] of which determine 32 or 64bits address

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When Avalon_MM address width = 64bits

'Number of address pages' and 'Size of address pages' disappear, and 'Address width of accessible PCIe memory space' appears

If I set Address width of accessible PCIe memory space = 22, I read the address width of 'txs interface' is 22bits. Obviously no paging or only one page.

Now I guess, PCIe address[21:0] are identical with qsys address[21:0]

But how about PCIe address[31/63:22]? And how about the PCI address width, 32 or 64 bits? Something fixed or by address translation table entry #0?

Section A.4.10 is for 32 bit addressing only, and it said 'If you select 64-bit addressing the bridge does not perform address translation.'

Regards,

Jiang Wanli

[Nathan_R_Intel]

Hie Jiang Wanli, My apologies for responding after almost a month. I posted a reply on 1st July but seems like it did not get posted. My apologies on that. I will retype my previous post Yes, you are correct, the Address Translation Table is only available when Avalon-MM address width is 32 bits. Your testing is correct. My previous note was misleading to mention that Address Translation Table is also available for 64 bits. As described in our user guide Section A.4.10, no address translation is available when using Avalon-MM address width = 64 bits. Also I can confirm that only one address page is available when using AVMM address width = 64 bits. Hence, thats the reason for your following observation: "Under Avalon-MM settings tab, 'Number of address pages' and 'Size of address pages' appear, and 'Address width of accessible PCIe memory space' disappears" So when using AVMM address width = 64 This is my response to the following questions: Question for using AVMM address width = 32; If I set Number of address pages = 16 and Size of address pages = 64KBytes(16 bits), from Component Instantiation \ Compilation Info \ Signals & Interfaces, I read the address width of 'txs interface' is 20bits. That is 64KB * 16 = 1MB. On qsys side: address[15:0] are passed through and become PCIe address[15:0] address[19:16] select one from the 16 address translation table entries address[31:20] are determined by Assign Base Addresses On PCIe side: address[15:0] are identical with qsys address[15:0] address[31:16]/address[63:16] come from the selected address translation table entry, b[1:0] of which determine 32 or 64bits address Response: Your interpretation of the address translation table seems correct per my understanding. Question for using AVMM address width = 64: Now I guess, PCIe address[21:0] are identical with qsys address[21:0] But how about PCIe address[31/63:22]? And how about the PCI address width, 32 or 64 bits? Something fixed or by address translation table entry #0? Response: When using Address width of accessible PCIe memory space = 22, the PCIE address width of accessible PCIe memory space is 22bits. Yes,[21:0] is the PCIe address bits. Hence, the remaining PCIe address [31/63:22] is not accessible. Your PCIe address width is 64 bits buts only 22 bits is accessible. Its not fixed by any address translation table. Regards, Nathan

[万江]

Hi Nathan,

Thank you very much.

Now I still not clear how high PCIe address bits are determined, when Address width of accessible PCIe memory space is LESS than 64.

My solution is:

set AVMM address width = 64, and set Address width of accessible PCIe memory space = 64

writing a dedicated component to master txs point-to-point, it controls all 64 address bits of txs.

at the same time, the component is an MM slave too. the host will tell it where the dma buffer is thru a BAR.

the txs can NOT be connected to the main QSYS directly, because it will occupy ALL address space.

it does work, but it looks a little stupid.

Regards

Jiang Wanli

[Nathan_R_Intel]

Jiang,

Could you send me your design achieve (.qar) so, I can understand what you mean by TXS cannot be connected to main QSYS directly. Currently, from your description alone its vague.

Also when you changed your AVMM address width = 64 bi with PCIE address width of accessible PCIe memory space is 64 bits; it allows all 64 bits to be accessible.

Regards,

Nathan