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Hello,
I'm testing PCIe on a C10 devkit by quartus 18.0pro. Application interface type = Avalon_MM(no DMA), Avalon_MM address width = 32bits.
Under Avalon-MM settings tab, why size of address pages can NOT be set to between 17-21bits(128KB-2MB)?
By the way, if Avalon_MM address width = 64bits, and address width of accessible PCIe memory space = 20. When an avalon-mm to PCIe transaction occurs, what are higher 42 address bits on PCIe? All zeroes?
Thanks
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Hi Nathan,
Thank you for your explanation
But according to my testing, I feel the Address Translation Table is available only when Avalon_MM address width = 32bits
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When Avalon_MM address width = 32 bits
Under Avalon-MM settings tab, 'Number of address pages' and 'Size of address pages' appear, and 'Address width of accessible PCIe memory space' disappears
If I set Number of address pages = 16 and Size of address pages = 64KBytes(16 bits), from Component Instantiation \ Compilation Info \ Signals & Interfaces, I read the address width of 'txs interface' is 20bits. That is 64KB * 16 = 1MB.
On qsys side:
address[15:0] are passed through and become PCIe address[15:0]
address[19:16] select one from the 16 address translation table entries
address[31:20] are determined by Assign Base Addresses
On PCIe side:
address[15:0] are identical with qsys address[15:0]
address[31:16]/address[63:16] come from the selected address translation table entry, b[1:0] of which determine 32 or 64bits address
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When Avalon_MM address width = 64bits
'Number of address pages' and 'Size of address pages' disappear, and 'Address width of accessible PCIe memory space' appears
If I set Address width of accessible PCIe memory space = 22, I read the address width of 'txs interface' is 22bits. Obviously no paging or only one page.
Now I guess, PCIe address[21:0] are identical with qsys address[21:0]
But how about PCIe address[31/63:22]? And how about the PCI address width, 32 or 64 bits? Something fixed or by address translation table entry #0?
Section A.4.10 is for 32 bit addressing only, and it said 'If you select 64-bit addressing the bridge does not perform address translation.'
Regards,
Jiang Wanli
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Hi Nathan,
Thank you very much.
Now I still not clear how high PCIe address bits are determined, when Address width of accessible PCIe memory space is LESS than 64.
My solution is:
set AVMM address width = 64, and set Address width of accessible PCIe memory space = 64
writing a dedicated component to master txs point-to-point, it controls all 64 address bits of txs.
at the same time, the component is an MM slave too. the host will tell it where the dma buffer is thru a BAR.
the txs can NOT be connected to the main QSYS directly, because it will occupy ALL address space.
it does work, but it looks a little stupid.
Regards
Jiang Wanli
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Jiang,
Could you send me your design achieve (.qar) so, I can understand what you mean by TXS cannot be connected to main QSYS directly. Currently, from your description alone its vague.
Also when you changed your AVMM address width = 64 bi with PCIE address width of accessible PCIe memory space is 64 bits; it allows all 64 bits to be accessible.
Regards,
Nathan

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