Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
14961 Discussions

In Platform Designer, Generate HDL fails for a hierarchical system that's two levels deep, but succeeds when the hierarchy is only one level.

RBash
Novice
236 Views

I have a hierarchical Platform Designer system (e.g., top_system) that has two levels, i.e., it has two instances of a subsystem (e.g., subsystem_0) which itself has four instances of another subsystem (e.g., subsystem_1). When I click Generate HDL for subsystem_0, HDL is generated successfully. But when I do the same for top_system, I face this error in the command line (and synthesis of the design fails later on because of it):

 

java.lang.IllegalArgumentException: subsystem_1: no such parameter: componentDefinition

 

And indeed in top_system.qsys file, there's no componentDefinition field for subsystem_1 instances, whereas in subsystem_0.qsys this field exists for instances of subsystem_1. What am I missing here?

Thanks in advance for your help.

0 Kudos
3 Replies
KennyT_Intel
Moderator
57 Views

Can you attached your *qsys files here? I would like to try and see if it is a bugs or not.

RBash
Novice
57 Views

Can I send the files privately to you?

KennyT_Intel
Moderator
57 Views

Sure, you may check your inbox.

Reply