- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
In Quartus Prime 18.1, even though I add the state machine (in the example that follows, is called "actual") in input Waveform.vwf, the simulation output does not show any value change in the state of the FSM. Here is the code of a sequence detector (1,1,0,1) implemented as Mealy:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pregunta1a is
port(clock: in std_logic;
data: in std_logic;
salida: out std_logic
);
end pregunta1a;
architecture mealy of pregunta1a is
type estado is (A,B,C,D,E);
signal actual: estado :=A;
signal futuro: estado;
begin
process (clock)
begin
if (clock'event and clock='1') then
actual <= futuro;
end if;
end process;
process (actual, data)
begin
futuro <= actual; -- default future state value
salida <= '0'; -- default output value
if (actual= A) then
if (data = '1') then
futuro <= B;
end if;
end if;
if (actual= B) then
if (data = '0') then
futuro <= A;
else
futuro <= C;
end if;
end if;
if (actual= C) then
if (data = '0') then
futuro <= D;
else
futuro <= E;
end if;
end if;
if (actual= D) then
if (data = '0') then
futuro <= A;
else
futuro <= B;
salida <= '1';
end if;
end if;
if (actual= E) then
if (data = '0') then
futuro <= A;
end if;
end if;
end process;
end mealy;
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
Please provide 'simulation waveform editor' screenshot from Quartus 18.1.
Just compile this VHDL code & Create the *.vwf file for same by referring below link,
https://www.youtube.com/watch?v=m1DhPAaKrzA
Regards,
Vicky
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Dear Vicky,
Here is the input waveform. Device selected: Cyclone IV E EP4CE6E22C6
You can see that I inserted the internal signal "actual", following Insert --> Node or Bus, the I pressed "Node Finder..", and then I filtered by "Design Entry (all names).
The selected signal is type "State Machine"
In the next message, you will see the output waveform.
Regards,
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Dear Vicky,
Here is the output waveform. I run timing simulation (not functional), in order to see the delays.
As you can see, the signal "actual" shows U, as undefined.
In old Quartus II version 9.1 you were able to combine the input file with the output file in a single file, and see the changes of "state machine" type of signals.
Is it possible in Quartus Prime 18.1 (I have standard version licensed) to combine input and output files in single input file as old Quartus II 9.1?
Is it possible to see the state machine changes in output file?
If I insert the flip-flops of this state machine I can see the changes of flip-flops, but is hard to follow, if there are many states, and if Quartus uses similar to "one hot" coding for the state machine.
Hope you can help me in finding a solution for this case.
Regards,
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
It may not be available in vector waveform file but you can see it in ModelSim simulation.
Regards,
Vicky

- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page