In verilog when the default case in a case statement is ignored by synthesis

[Altera_Forum]

I recently discovered that unless you specifically use the global assignment SAFE_STATE_MACHINE ON, the default case where the case statement is part of a state machine will be ignored. IE, not synthesized. Apparently, it has been this way for some time, but is news to me. In any event, I am trying to find out if the directive STATE_MACHINE_PROCESSING "USER-ENCODED" makes a difference. That is, does this directive force the tool to include the default case or not. Does anyone know?

[Altera_Forum]

I think what may be happening is that the compiler knows that the non-default cases cover all possible values of the state variable. Therefore it knows the default case will never be reached and correctly optimizes it away.

[Altera_Forum]

The default state encoding for state machines is 1 hot. This means with each state being a single bit, anything that is enabled by that state is simply connected to the single bit, hence the default case has no use.

[Altera_Forum]

Thanks for the reply, here is the problem. If timing is always met, the state variable will never have any unused states. The problem is timing is not always met in the communications world. You have external and internal plls acquiring lock and during that process, they may output a frequency that violates timing. I have a rule when coding logic. And that is you should be able to jam any set of values into any set of registers (other than micro processor controlled), let the system run and it will eventually return to normal. Logic that can get into a stuck state and stay there is very bad especially when it happens at a customer sight. Altera is touting an experiment where a car is being driven by a cyclone device. I would not want to be on the road with that car if the cyclone logic could get into a bad state and not recover. Altera calls it optimization, I call it re writing my code. A couple of days ago I looked at the difference in one of our chips between safe FSMs and unsafe. The additional logic usage was negligible and the design had over 100 state machines. On the other hand, this (unsafe) issue has caused a near stop shipment on one of our products.

[Altera_Forum]

They do spell out quite clearly in the quartus documentation what the state encoding does, and how it is chosen, but also that you are free to chose your own encoding scheme.

[Altera_Forum]

You may be free to choose your own encoding scheme, but the tools still need to honor the default case. It was put there for a reason. The tool should not arbitrarily decide it is not needed. Further more, for the user-encoded option, the documentation does not say one way or the other if the default is ignored when user-encoded is chosen. That was my original question and I still do not know for sure, however my suspicion is that unless safe is specified the default case will be ignored. Quartus should at least have included in the map.rpt that the default case is not reachable and will be ignored. We would have caught that allot easier than finding a blurb buried on page 914 of a 1000 page document.

[Altera_Forum]

This is an issue you probably want to take up with altera directly via mysupport.