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Inferring ROM for MAX 10 FPGA

Altera_Forum
Honored Contributor II
‎04-25-2018 03:32 AM
2,347 Views

Hi All, 

 

I am trying to get Quartus Prime Lite to infer a ROM using the on chip memory (M9K) for MAX 10 FPGA. Instead the ROM gets implemented using LEs which significantly blows up my resource utilisation. I am using the VHDL template in Quartus  

 

Edit - Insert Template - VHDL - Full Designs - RAMs and ROMs - Single-Port ROM 

 

I have also tried adding the romstyle attribute, but no luck. 

 

As an experiment, I changed the device to Cyclone IV and the ROM gets successfully implemented in on chip memory. 

 

I have searched online and a I came across a solution using MIF files - https://alteraforum.com/forum/showthread.php?t=54407 

 

However, this solution is too inflexible for me. I'd like to use VHDL rather than the tool's IP wizard. 

 

Wondering if anyone has a solution for me? This is driving me crazy. The same VHDL also gets successfully mapped to BRAM on Xilinx devices. Is this a bug in Quartus Prime for MAX 10 FPGAs? 

 

Regards, 

Singh
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Altera_Forum
Honored Contributor II
‎04-25-2018 09:28 AM
1,473 Views

A possible reason that you are using a "compact" MAX10 type that doesn't provide RAM initialization, e.g. SC type. Which device are you compiling the design for?

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Altera_Forum
Honored Contributor II
‎04-26-2018 06:55 AM
1,473 Views

Hi FvM, 

Thanks for your reply. 

It's 10M16SAU169C8G 

 

Regards, 

Singh
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