Inferring ROM module

Altera_Forum · ‎02-28-2010

Hello everyone, I am currently designing 8-bit resolution Sinusoidal Wave Generator. I chose the look-up table method which needs a ROM module (256x8bit). I am using verilog coding and synthesize using Quartus II 9.1 on cyclone II device family. Here is my sub-module for the look-up table :

module LUT256 (
ADDR,    // Address input
DataOut, // Data output
RE,      // Read Enable 
CE       // Chip Enable
) /* synthesis romstyle = "M4K" */;  
input  ADDR;
output  DataOut; 
input RE,CE; 
(* romstyle = "M4K" *) reg  mem  ;  
wire  DataOut;
      
assign DataOut = (CE && RE) ? mem : 8'b0;
initial begin
  $readmemb("sine_value.list", mem);  // sine_value is pre-calcualted value
end
endmodule

The problem is, when I view the Technology Map Viewer (post mapping), the sub-module doesn't synthesize into ROM but instead into logic cells. RTL Viewer shows that the sub-module synthesized into memory module though. I also changed the appropriate settings in Quartus II analysis&synthesis settings for ROM/RAM to infer ROM/RAM module. Can someone please explain how to fix this problem. Thank you in advance.

Altera_Forum · ‎02-28-2010

I think you need to add a clk. I had this problem too and the solution was to make the memory bigger, so you might want to try that as well.

Altera_Forum · ‎02-28-2010

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I think you need to add a clk.

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Exactly. View the Verilog language templates in Quartus editor, they have examples of RAM and ROM inference. The requirements are also explained in detail in the Quartus software handbook.

Altera_Forum · ‎03-01-2010

Thanks everyone for helping me. I managed to solve the problem by adding clock to the module. Here's the final code :

module LUT256DFF (
Clk,
ADDR,    // Address input
DataOut, // Data output
RE,      // Read Enable 
CE       // Chip Enable
) /* synthesis romstyle = "M4K" */;  
input Clk;
input  ADDR;
output  DataOut; 
input RE,CE; 
           
(* romstyle = "M4K" *) reg  mem  ;  
reg  DataOut;
always @ (posedge Clk)
begin      
  if (CE && RE)
    DataOut <= mem;
end
initial begin
  $readmemb("sine_value.list", mem);  // sine_value is pre-calcualted external memory file
end
endmodule

It will synthesize to 2048bits of RAM (altsyncram). One question, is this RAM has the same attribute with the cyclone II's M4K ROM ?