choosing default synthesis for arithmatic operators

[Altera_Forum]

Hello all, 

 I have some verilog code that has many basic arithmatic symbols in it (+,-,*,/). Obviously the simple and perhaps also wise thing to do is to replace such operators with Mega-Wizard modules but I have many of them and not allways in the same bit size. my problem is this: most of the calculations are with signed (2's complement) numbers and I want to set the default synthesis of operators as signed operations. this way I would know for sure - no matter what board I'm using that when I write a+b it's synthesized as signed adder.  PS the same goes also to simulations in Modelsim if anyone knows.  Thanks, Ayal

[Altera_Forum]

Have you taken a look at the templates menu in Quartus II? It has a bunch of arithmetic templates for Verilog and VHDL that might show you how to code those operators to ensure you get what you want. 

 Have a source file open and then go to "Edit" --> "Insert Template" --> then navigate to the language and logic type you want.

[Altera_Forum]

--- Quote Start ---  Hello all,  I have some verilog code that has many basic arithmatic symbols in it (+,-,*,/). Obviously the simple and perhaps also wise thing to do is to replace such operators with Mega-Wizard modules but I have many of them and not allways in the same bit size. my problem is this: most of the calculations are with signed (2's complement) numbers and I want to set the default synthesis of operators as signed operations. this way I would know for sure - no matter what board I'm using that when I write a+b it's synthesized as signed adder.  PS the same goes also to simulations in Modelsim if anyone knows.  Thanks, Ayal  --- Quote End ---    Hi,  have a look to the improvements coming with Verilog 2001. As far as I know signed and unsigned is directly supported. Have a look to :  http://www.asic-world.com/verilog/verilog2k1.html  Kind regards  GPK

[Altera_Forum]

Thanks!  

 silly me, this is so simple...