Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "in" into its bus
The right number of resources seem to be used but I find this worrying.
In essence I'm using a macro to unpack a linear array into a 3D array:
wire [1:0] in [1:0][1:0];
The error is an "info" as opposed to an error. Is this significant?
Is there a way to eliminate this "info"?
In a Verilog Design File (.v) or VHDL Design File (.vhd), you used the specified multidimensional array. Because the EDA Netlist Writer cannot regroup the multidimensional array into its bus, output file generation may result in a degenerate bus. However, logic synthesis is not affected.
To avoid receiving this message in the future, edit the design to use a one- or two-dimensional array. Otherwise, no action is required.
Many thanks for the fast reply. This would be so much neater if I could retain the 2D array.
My concern was that this would affect synthesis and good to know that it won't. I can live with a warning!
Sure. I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you