Initializing RAM from file,getting ZZZ at some memory locations

Altera_Forum · ‎12-23-2012

Hi,

I am initializing RAM from a .txt file, which looks like this:(the first word in a line is a hex address, and the other word is the binary data that i store in that location)

00000000 10000011101100001101000000000011

00000004 11100011111100000000000000000011

00000008 01000011101100000001000000000111

0000000C 10100011101100000010000000000101

.

Sometimes everything works ok, but if i write a longer init code, starting after some 15-20 locations, the first 3 bits dont get read correctly? :

.

ZZZ00011101100aa0010000000000101

ZZZ00011001100000010000000000101 >>>>>>>>>>>> I get ZZZ for the first 3 bits, for every mem location to the end...and this doesnt happen always.

ZZZ00011111000000010000000000101

.

here is the VHDL code i use for RAM:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_textio.all;
use STD.textio.all;
library work;
use work.conv_package.all;
entity RAM is
generic (wordLength:integer := 32; addressLength : integer := 32; size : integer := 16);
port (
		init, we, rd, clk : in std_logic;
		ABUS: in std_logic_vector((addressLength - 1) downto 0);
		DBUS_in: in std_logic_vector((wordLength - 1) downto 0);
		DBUS_out: out std_logic_vector((wordLength - 1) downto 0)
);
end RAM;
architecture ins_ram of RAM is
	type memory_array is array (0 to size-1) of 
		std_logic_vector((wordLength - 1) downto 0);
	
                signal memory : memory_array;	--this is RAM memory
	
begin
	write:process (clk)
		file input_ins : TEXT open READ_MODE is "test_inst.txt";
		
		variable file_line : LINE;
		
		variable ins_addr: std_logic_vector (31 downto 0);
		
		
	begin
		if (clk'event and clk = '1') then
			
			-- write to memory
			if (we = '1') then
				memory(convert(ABUS)) <= DBUS_in;
				
			-- initialize memory locations
			elsif (init = '1') then
					
					-- initialize instruction memory
					loop
						exit when endfile (input_ins);
						readline(input_ins, file_line);
						extract(file_line, ins_addr, ins_data);
						memory(conv_integer(ins_addr)) <= ins_data;
					end loop;		
					
				
			end if;
			
		end if;
	end process write;
	with rd select
	DBUS_out <= memory(convert(ABUS)) when '1',
	(DBUS_out'range => 'Z') when others;
	
end;

The convert function converts the hex address, and it works correctly, and so does the extract(which gets the hex address and the binary data). (i can out the code if you wish)

Has anyone had a problem like this one? Thanks for your help!