I want simulate the post syntesis netlist with NCSIM. I have some memory implemeted with some 4k ram block and i need to initialize them.On megawizard blocks i use mif and hex files, but in simulation don't run. How can I do? On the Altera web site i find thishttp://www.altera.com/support/software/nativelink/simulation/ncsim/eda_pro_ncsim_func_sim.html but i don't understand were put the line with parameter. My memory are always not initialized. Someone can help me? Thanks I work in verilog. I need to do something in quartus?
Where the web page you listed says "functional simulation", that means simulating with your RTL files. Your post said "simulate the post synt[h]esis netlist." If you are simulating with a .vo generated by Quartus, see the timing simulation link on the web page you listed.With a .vo, the memory initialization data will be inside that file. The simulator won't use .mif or .hex files. (See http://www.alteraforum.com/forum/showthread.php?p=2154#post2154.)