Input wants to be assigned and constrained as Clock

[Altera_Forum]

Hi, 

I'm running mad with this:  I've got tree inputs of asynchronous Signals. These Signals are the ABZ-Signals of a device which meassures a movement (I just don't know how it is called in english, sorry).  After the signals arrive in my design, I have to digitally filter them:   Dig_Filter: process (Clk_IN, Input_A_IN, Input_B_IN, Input_Z_IN, sig_A, sig_B, sig_Z, sig_Filter_A, sig_Filter_B, sig_Filter_Z) begin if (falling_edge(Clk_IN)) then sig_Filter_A(0) <= Input_A_IN; sig_Filter_A(1) <= sig_Filter_A(0); sig_Filter_A(2) <= sig_Filter_A(1); sig_Filter_A(3) <= sig_Filter_A(2); sig_Filter_A(4) <= sig_Filter_A(3); if (sig_Filter_A = "11111") then sig_A <= '1'; elsif (sig_Filter_A = "00000") then sig_A <= '0'; else sig_A <= sig_A; end if; sig_Filter_B(0) <= Input_B_IN; sig_Filter_B(1) <= sig_Filter_B(0); sig_Filter_B(2) <= sig_Filter_B(1); sig_Filter_B(3) <= sig_Filter_B(2); sig_Filter_B(4) <= sig_Filter_B(3); if (sig_Filter_B = "11111") then sig_B <= '1'; elsif (sig_Filter_B = "00000") then sig_B <= '0'; else sig_B <= sig_B; end if; sig_Filter_Z(0) <= Input_Z_IN; sig_Filter_Z(1) <= sig_Filter_Z(0); sig_Filter_Z(2) <= sig_Filter_Z(1); sig_Filter_Z(3) <= sig_Filter_Z(2); sig_Filter_Z(4) <= sig_Filter_Z(3); if (sig_Filter_Z = "11111") then sig_Z <= '1'; elsif (sig_Filter_Z = "00000") then sig_Z <= '0'; else sig_Z <= sig_Z; end if; else sig_Filter_A <= sig_Filter_A; sig_Filter_B <= sig_Filter_B; sig_Filter_Z <= sig_Filter_Z; sig_A <= sig_A; sig_B <= sig_B; sig_Z <= sig_Z; end if; end process Dig_Filter;  This is all what is done to the ABZ-Signals. And this is my Problem: I always get the Warnings: Warning (332060): Node: Encoder_A was determined to be a clock but was found without an associated clock assignment. Warning (332060): Node: Encoder_B was determined to be a clock but was found without an associated clock assignment. Warning (332060): Node: Encoder_Z was determined to be a clock but was found without an associated clock assignment. (Encoder_A /B /Z are the Input Pins)  I have tried to use the "set_false_path" assignment, but the Warnings didn't vanish. Quartus and TimeQuest always analyze them as Clocks.:mad:  How can I get rid of this stupid clock determination? I just want them to be simple Inputs and no clocks anymore.  Thanks Steffen  PS: I also have this Problem with some internal signals which are control-signals between some IP-Cores

[Altera_Forum]

encoder_A in the error message is not part of posted code. You need to post the relevant code

[Altera_Forum]

Hi kaz, 

 I mentioned Encoder_A, _B and _Z. These are the names of the Pins feeding the Input Ports Input_A_IN, Input_B_IN and Input_Z_IN.  But I've forgotten something: In the Path from the Input-Pins (Encoder_A /_B /_Z) to the Input Ports (Input_A_IN, Input_B_IN and Input_Z_IN) of the Code above are an AND and an OR to switch off the Signals from the Input-Pins and activate a simulator which is capable of generating the ABZ-Signals internally (For testing purposes).  https://www.alteraforum.com/forum/attachment.php?attachmentid=8594

[Altera_Forum]

I assume it must be you are clocking registers on these inputs somewhere after pins.

[Altera_Forum]

Maybe, but how? The two Gates and the Code above are the only connection to those Input Signals.

[Altera_Forum]

Why not post the code so we can have a proper look? 

 And also - its very bad practice to have an "else" clause next to a clock. You get away with it because you just tell the code to hold the value, but if there was anything else in there the synthesisor would throw and error for bad synchronous description. You also only need the clock signal in the sensitivity list, the rest are redundant (and technically slow your simulator down).

[Altera_Forum]

your code doesn't show edge triggering on these inputs. Though you don't need to put anything but clk_in inside sensitivity list and you don't need the else at the end 

but these have nothing to do with the issue.

[Altera_Forum]

Some ideas: 

- Look for messages in synthesis about latches being inferred. It's hard to mistakenly create a register, but easy to create latches. - Change your file to SystemVerilog and use the always_ff, always_comb structures. (I'm not sure what synthesis does if make a mistake, and not certain it errors out, but conceptually I like these constructs, especially when getting started) - Launch TimeQuest and type "derive_clocks -period 10.0". This puts a 10ns clock constraint on everything that TQ thinks is a clock. (Note that you should never do this in a real design, but this is for a test). Then run Report Clocks in the task to see which clocks are created. I assume these will show up as clocks. If they do, run:  report_timing -setup -to_clock <insert_clk_name_here> -detail full_path -panel_name "to clock"  report_timing -setup -from_clock <insert_clk_name_here> -detail full_path -panel_name "from clock" This should show paths with registers driven by that clock. - Go to the RTL view and trace forward from that signal to all the destinations. There should be a register or latch showing up.

[Altera_Forum]

I agree with kaz and Tricky, maybe the problem comes from another part of the code. 

Anyway, just to talk... I think the statement after "else" are useless. They teached me that if you enter a process, that is a register/flip-flop. So if there is a condition (if ... ecc ecc) the register will memorize a new value for a signal, but if the condition will not occur that register will store the old value automatically.

[Altera_Forum]

Hmmm, Code, you want code. OK here is all I can give you: 

 https://www.alteraforum.com/forum/attachment.php?attachmentid=8595   As I see it NOW: The three wires which are leading down from the ABZ-Wires, goto some counters, which are counting the POSITIVE EDGES of the Signals.  MEA CULPA  This is why Quartus thinks these are clocks. OK, in this case I have to change the counters to sample the Inputs and counting a change in a 2Bit shift-register.  Sometimes speaking about a Problem helps also to solve the Problem.  Thanks