Instantiation Components Compile error

[Altera_Forum]

Hi, 

 I'm new to Quartus 6.1 Web Edition software. I bought the CYCLONE FPGA Starter Board and tries to learn how to use Quartus 6.1 that came with the board.  The problem I'm having is with my functions, parts and component libraries. For example, when I try to compile the following VHDL code which is a FULL_ADDER, I keep getting the following error message :   vhdl error at full_adder.vhd(18): object "xor_3" is used but not declared  Before compiling the code, I've included the necessary libraries during the project creation. Despite everything I've tried, I'm still getting the same error message. It does not matter whether I include or not the use clauses for the libraries needed in my root page, I get the same error message. It just does not see my instantiated components.  I've to stress that the same code compiles and runs on ORCAD FPGA Simulation, but not on QUARTUS. Why is it so difficult to get things run normally with Quartus while they run smootly on all other simulators I've been working on so many years? - Strange...  I've followed all Quartus recommandations on the subject and I'm still anable to solve this issue.  Thanks to show me what to do in order to use my libraries with QUARTUS. Below is the program without the parts and components libraries needed.  library ieee; use ieee.std_logic_1164.all; -- I do not have to use the parts and components libraries below with ORCAD. --library parts_lib;  --use parts_lib.all; --library comp_pkg; --use comp_pkg.all; ---------------------------------------------------------------------- entity full_adder is port(  a, b, cin : in std_logic;  sum, co : out std_logic  ); end full_adder; ---------------------------------------------------------------------- architecture full_adder_arch of full_adder is  signal sig1, sig2, sig3 : std_logic; begin  U1 : component xor_3 port map(  x1 => a, x2 => b, x3 => cin,  y => sum  );    U2 : component and_2 port map(  x1 => a, x2 => b,  y => sig1  );    U3 : component or_2 port map(  x1 => a, x2 => b,  y => sig2  );    U4 : component and_2 port map(  x1 => sig2, x2 => cin,  y => sig3  );     U5 : component or_2 port map(  x1 => sig1, x2 => sig3,  y => co  );  end full_adder_arch;

[Altera_Forum]

Any libraries you reference in VHDL code must be included in your project files list, and they must be listed prior to any VHDL file that references them. To do this in Quartus, 

 (1) Select "Assignments / Settings / Files" and make sure your VHDL packages (aka libraries) and your top-level VHDL file are listed in the files list. If any file is missing, select the "..." button and browse to that file then select "Open" and "Add" to place it in the list.  (2) Left-click on files then use the "Up" and "Down" buttons in Quartus to change the file orders. Libraries should be on the top of the list, and the top-level source file on the bottom.

[Altera_Forum]

Hi endian, 

 I've tried all these and still it's not working. Maybe the mistake I'm doing resides in the extensions I use for the files or there's something I'm not still aware of QUARTUS software on the way it handles files. Here are the files I'm using for the test :  The top level file is : full_adder.vhd The parts library file (which contains entity-architecture for all the parts) : parts_lib.vhd The component library file is : comp_pkg.vhd.  So as you see, they all have the same .vhd extension but different names.  When I try to read the parts_lib.vhd and comp_pkg.vhd files from the library folder, I do not see them. I only see the directory where they reside. Therefore, I enter their names manually in the order you've specified and all other possible left orders. But I'm still getting the same error message. You've mentioned aka files. Does this mean the library files unstead being terminated with an .vhd extension, they should have an .aka extension?.   This is new to me as I've always used the .vhd extension files on every file with other softwares I've used until now.  Thanks for trying to help.

[Altera_Forum]

Continue using the .vhd extension. That is not a problem. 

 Don't use the "Libraries" portion of the project settings to specify your VHDL packages. A user library extends the search path beyond the project work directory and the built-in libraries, but does not force the tool to elaborate your VHDL packages.  You need to list the .vhd files in the project's "Files" area as mentioned above, not "User Libraries".

[Altera_Forum]

Thanks again endian, 

 I guess we've burned all possible options. I've removed all the packages from the project library and included them in the file portion of the project (assignment\settings\files), but for some reason, I'm still getting the same compile error message. I've the feeling the comp_pkg.vhd have not for some reason been compiled.  Of course, since it works for other people, being used to work with more straithforward softwares, there must be obviously something I'm doing wrong, but I can't for now put my finger on.  But thanks for trying to help. I'll still continue to try different options and If I can get it to work, I'll let you know what I did (if you don't hear from me, then I'll be still juggling with the software).  Many thanks again for your time.

[Altera_Forum]

Look in the "Processing" tab of the messages screen near the bottom of your QuartusII window (ALT-3 toggles this window on/off). You should see messages relating to the processing of your design including which file is being processed. Make sure it is reading in all of your files, and if not then look for messages stating why.

[Altera_Forum]

Hi endian, 

 Here's the message I get from the processing tab. It did find the right numbers of entity-architecture in the parts_lib.vhd file, and a total of 14 design units which I assume to be the 7 design units in the parts_lib.vhd file + the number of design units of the comp_pkg.vhd file, although not clearly stated in the processing tab. Again, it stop compiling at the first component unit which the compiler states being used but not declared as if the comp_pkg.vhd file is not being seen by the compiler although I've included it with files.   One think that worth to be mentioned. The working directory is one that I've created on a different folder named D:\projects\vhdl\Full_Adder\ and the top level file and the two others (parts_lib.vhd and the comp_pkg.vhd) are in the same directory.   Again, thanks for your help.  Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis  Info: Version 6.1 Build 201 11/27/2006 SJ Web Edition  Info: Processing started: Tue Jun 26 17:15:41 2007 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off full_adder -c full_adder Info: Found 1 design units, including 0 entities, in source file comp_pkg.vhd  Info: Found design unit 1: comp_pkg Info: Found 14 design units, including 7 entities, in source file parts_lib.vhd  Info: Found design unit 1: and_2-and_2_arch  Info: Found design unit 2: and_3-and_3_arch  Info: Found design unit 3: nand_2-nand_2_arch  Info: Found design unit 4: nand_3-nand_3_arch  Info: Found design unit 5: or_2-or_2_arch  Info: Found design unit 6: xor_2-xor_2_arch  Info: Found design unit 7: xor_3-xor_3_arch  Info: Found entity 1: and_2  Info: Found entity 2: and_3  Info: Found entity 3: nand_2  Info: Found entity 4: nand_3  Info: Found entity 5: or_2  Info: Found entity 6: xor_2  Info: Found entity 7: xor_3 Info: Found 2 design units, including 1 entities, in source file full_adder.vhd  Info: Found design unit 1: full_adder-full_adder_arch  Info: Found entity 1: full_adder Error (10482): VHDL error at full_adder.vhd(19): object "xor_3" is used but not declared Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings  Info: Allocated 129 megabytes of memory during processing  Error: Processing ended: Tue Jun 26 17:15:43 2007  Error: Elapsed time: 00:00:02 Error: Quartus II Full Compilation was unsuccessful. 1 error, 0 warnings

[Altera_Forum]

Hi, 

 I've moved the component design units from the comp_pkg.vhd files into the architecture of the top level file and now it compiles correctly. Therefore, the compiler sees the parts_lib.vhd file but odd enough not the comp_pkg.vhd file although it's been included in the file section.

[Altera_Forum]

Hi, 

 I've finally got it. I had to use specifically a use clause of the comp_pkg.vhd (component packaging) in the main Top Level vhd file, but not necessarily the parts_lib.vhd file which contains the entity-architecture parts units. It seems that we have to use a use clause in the main file when a file to be included contains a package definition. The latter apparently cannot be read and compiled when inserted in the project file section.  Thanks again for trying to help.  PS : I just don't know then what's the use of the user library file if nothing happens when the libraries are inserted there.

[Altera_Forum]

Hi, 

I'm new on VHDL and QUARTUS II. I receive errors from compilation because of 'ELSE' in my code. I don't understand why Quartus II don't recognize ELSE, WAIT FOR , and WHEN . Please help me, I want know. This is one of my code which don't compile successfuly :  LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all;  ---------------------------  ENTITY compt IS  PORT (  C: IN STD_LOGIC;  V: IN STD_LOGIC;  A: OUT STD_LOGIC  ); END compt;  ---------------------------  ARCHITECTURE arc OF compt IS BEGIN  IF (C'EVENT AND C='1' AND V='0') THEN  A <= '1';  ELSE   A <= '0';  END IF;  END arc;  Error (10500): VHDL syntax error at compt.vhd(21) near text "IF"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement Error (10500): VHDL syntax error at compt.vhd(21) near text "THEN"; expecting "<=" Error (10500): VHDL syntax error at compt.vhd(23) near text "ELSE"; expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a concurrent statement Error (10500): VHDL syntax error at compt.vhd(25) near text "IF"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"   Really thank you by advance Pascale

[Altera_Forum]

When you start writing VHDL code from the scratch, you should either have a basic understanding of the syntax and semantics or expect some unsuccessful attempts. 

 The problem is, that the error message not necessarily tells the basic error. In your example, it's the simple fact that you can't use sequential statements outside a process. Did you already experience the language templates in Quartus editor (accessible through right mouse-key context menu). They may be a good starting point for some VHDL exercises.  If you put a sequential (process) block around your code, it still can't work this way. But that's another story. You can imagine it as a flip-flop with permanently enabled reset. Setting the output to '1' by the clocked input has no effect at all then.

[Altera_Forum]

Thank you a lot for your response. 

Actually , I try every ways it's possible. I rely on a good book 'Circuit Design with VHDL' of Volnei A.Pedroni. The fact I don't understand is :"Why Quartus II failed compilation with based code as 'WHEN' 'WAIT' or 'ELSE' ?" Thank you again.

[Altera_Forum]

If you use these constructs as in Pedronis examples, Quartus will accept them. You should read particularly chapter 5 and 6.

[Altera_Forum]

I am very sorry, I don't know what is Pedronis examples. Can you explain me where I can find it? 

Thank you a lot.

[Altera_Forum]

Oups, I understand the s.

[Altera_Forum]

Try this, it works. 

:)  -----------------------------------------  LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all;  ENTITY compt IS PORT ( C, V :IN std_logic; A :OUT std_logic); END ENTITY compt;   ARCHITECTURE arc OF compt IS  begin process(C) begin  if (C'EVENT AND C='1' AND V='0') then  A <= '1';  else  A <= '0';   end if; end process; end arc;  -----------------------------------------

[Altera_Forum]

--- Quote Start ---  If you put a sequential (process) block around your code, it still can't work this way. But that's another story.  --- Quote End ---  Of course you are free to ignore any previous suggestion, but you should at least try to compile the code. That what Quartus thinks about it:   --- Quote Start ---  Error (10818): Can't infer register for "A" at compt.vhd(17) because it does not hold its value outside the clock edge Error (10822): HDL error at compt.vhd(17): couldn't implement registers for assignments on this clock edge  --- Quote End ---  

[Altera_Forum]

Yes, you are right FvM. What I have done is "Analyze Current File" without compiling and it seemed to have solved the problem. 

I tried now to compile and I have received those messages. I am a Verilog user and I am taking the opprtunity to learn some VHDL. :)

[Altera_Forum]

Yes, the present unreasonable construct wouldn't be possible in a Verilog always @ (posedge C) block. 

 Unfortunately, I don't know what's the intended behaviour, under which conditions the action A <= '0'; shall be peformed. A possible synthesizable variant would be this: if C'EVENT AND C='1' then if V='0' then A <= '1'; else A <= '0'; end if; end if;

[Altera_Forum]

YES, really thank you, it works. 

Now, can I use " C'EVENT and C='1' " AND "C'EVENT and C='0' " on the same code?

[Altera_Forum]

because Altera gives me this error : 

 Error (10819): Netlist error at compt.vhd(26): can't infer register for A because it changes value on both rising and falling edges of the clock  maybay it's not possible...?