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Altera_Forum

Honored Contributor I

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12-04-2017
02:25 AM

1,815 Views

Instantiation Errors

Hello,

I'm trying to reference my full adder module inside another module but seem to be getting lost somehow in the referencing. I keep getting the error Checker 'Full_Adder' not found. Instantiation 's' must be of a visible checker. the code I have is: always @(posedge clk) begin if (reset==1) // reset isn't pressed begin if (enable==1) //enable is active begin case ({ALU_OP}) 2'h0 : D = A & B; 2'h1 : D = A | B; 2'h2 : Full_Adder f(A,B,D,C); 2'h3 : D = A * B; endcase end end end endmodule module Full_adder(a,b,answer,carry_out); //inputs input [2:0] a,b; //outputs output [2:0] answer; output carry_out; //wires wire carry_out; wire [2:0] carry; genvar i; generate for(i=0;i<2;i=i+1) begin: generate_N_bit_Adder if(i==0) half_adder f(a[0],b[0],answer[0],carry[0]); else full_adder f(aLink Copied

3 Replies

Altera_Forum

Honored Contributor I

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12-04-2017
08:40 AM

378 Views

Altera_Forum

Honored Contributor I

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12-04-2017
11:53 AM

378 Views

Hi,

Take care on suggested point about instantiation.```
half_adder f(a,b,answer,carry);
full_adder f(a,b,carry,answer,carry);
full_adder f(a,b,carry,answer,carry);
```

etc. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
Altera_Forum

Honored Contributor I

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12-04-2017
12:50 PM

378 Views

Hi,

The issue is the module names. Verilog is case sensitive. In the module you've used "Full_adder" and in the instantiation you've used "Full_Adder" . The tool will think this "Full_Adder " is another module. Just be careful about the module names. Plus as pointed out earlier, instances are not like C functions. Use named instances instead of positional as this will reduce the chances of errors.Topic Options

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