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Instantiation of one module disturbing other module functionality

Altera_Forum
Honored Contributor II
‎03-17-2015 04:32 AM
1,105 Views

Hello, 

 

Am using Cyclone V device (5CSEBA5U23). I written verilog code for ADC module and it is instantiated in top module,its working well... When i have added other module which for reading the encoder data, my ADC module behavior changed. when i commented encoder module instantiate, ADC module is working well. For ADC Module and Encoder module no signals are in common. 

 

How can i solve the problem?
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Altera_Forum
Honored Contributor II
‎03-17-2015 08:55 AM
422 Views

Have you checked the timing of your design? The quick way is to look at Compilation Reports in Quartus under the section "TimeQuest Timing Analyzer". Is it getting worse when you instantiate both modules?

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