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I am using an integer to count pulses and then need to give it to an 7 Segment display.
Can I use the Integer variable as an array directly , and read each place's value ? The highlighted statement gives an error. ----------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; entity newcounter is Port ( clk : in std_logic; HEX0,HEX2, HEX1: out std_logic_vector(6 downto 0):= "1111110" ); end entity; architecture Behavioral of newcounter is signal temp0,temp1,temp2: integer :=0; begin process (clk) is type seven_seg is array ( 0 to 9 ) of std_logic_vector ( 6 downto 0 ); constant decode : seven_seg := ( "1000000" , "1111001" , "0100100" , "0110000" , "0011001" , "0010010" , "0000010" , "1111000" , "0000000" , "0010000" ); variable count: integer:=0; begin if rising_edge(clk) then count := count + 1; end if; temp0 <= count(0);HEX0 <= decode( temp0); end process; end Behavioral;
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no, an integer is not an array, so you cannot do this. And anyway, you could not take an integer from it even if you could - it would be a single bit.
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to get access to the single bits, you need to convert it to an array type - easiest would be signed or unsigned:
signal temp : std_logic; temp <= to_signed(count, 1)(0);- Mark as New
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I get the following error -
Error (10476): VHDL error at newcounter.vhd(32): type of identifier "temp0" does not agree with its usage as integer type. The snippet is temp0 <= to_signed(count, 1)(0); HEX0 <= decode(temp0); with the rest same as above.- Mark as New
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Hi, read/understand the error and look at the code :cool:
remove temp0 form the line "signal temp0,temp1,temp2: integer :=0;" add the line "signal temp : std_logic;" (from Tricky) just under And writetemp <= to_signed(count, 1)(0);
HEX0 <= decode(temp0);
outside the process OR write
process (clk) is
-- variable declarations
begin
if rising_edge(clk) then
count := count + 1;
temp0 <= to_signed(count, 1)(0);
HEX0 <= decode( temp0);
end if;
end process;
By this last way, you will produce register and then latence : count --> temp0 --> decode (outside the "if rising_edge(clk)...end if;", you will get very unexpected results !) You need to be more rigorous :-P and get good basis in VHDL (Altera vhdl style guide line....)
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