Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15336 Discussions

Intel HLS 18.1 C++/RTL result does not match



I am having this simple C++ program that is triggering different C++ and RTL simulation result. I called build.bat test-x86-64 to generate the C++ executable, and build.bat test-fpga to generate the RTL executable. The C++ result is B, whereas the RTL simulation result is 0. I am not really sure what is causing the difference here. Any idea would be helpful! Thanks!



#include <stdint.h>
#include <stdio.h>

static volatile int32_t a[6][1][7] = {{{0L,1,2,3,4,0L,1}},{{1,(-3L),(-1L),1,1L,6L,(-3L)}},{{1,0L,0L,1,0L,0L,2}},

/* ---------------------------------------- */
component unsigned int result() 
    int i, j, k;
    a[5][0][0] = 1;
    a[5][0][0] = a[5][0][0];
    a[5][0][0] = 1;
    a[5][0][0] = a[5][0][0];
	unsigned int tmp = 1;
    for (i = 0; i < 6; i++)
        for (j = 0; j < 1; j++)
            for (k = 0; k < 7; k++)
	            tmp ^=a[i][j][k];
	return tmp;

int main(void) 
	unsigned int resultOut = result();
	printf("%X\n", resultOut);
	return 0;



0 Kudos
1 Reply

Hi ,

Please try with latest version 20.2 of HLS. We have tested the code which you have provided and the results are consistent. We are getting B on both scenarios.

Thanks and Regards