I am using Intel P tile avalon MM PCIe Express and Intel PCIE 512 bit controller
Warning(16735): Verilog HDL warning at intel_pcie_dma_hwtcl.sv(329): actual bit length 174 differs from formal bit length 160 for port "desc_rdata_o"
Warning(16735): Verilog HDL warning at inigo_pcie_intel_pcie_dma_0.v(64): actual bit length 32 differs from formal bit length 174 for port "dma_wrdm_tx_data_i"
I am getting these kind of warning while synthesis
mainly its because of IP parameterization of PCIe DMA
here VFNUM address width
PFNUM address width
how can i fill these columns ?
anyone please explain with example
These warnings are come with the example design, and we have reported it to our engineering team. For this moment, you may safety ignore it, and we will improve it in the future version.
I have generated an example design by using v20.3, and also observed quite a number of "lost fan out" from the IP or DMA controller. Since this happens within the internal IP logic, and those logic might be reserved or not actually using, therefore, there is no way for us to eliminate it. You can just safety ignore it as we don't expect it will impact the IP hardware functionality.
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