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15546 Discussions

Intel PCIE 512bit Controller

10
Beginner
406 Views

Hi,

I am using Intel P tile avalon MM PCIe Express and Intel PCIE 512 bit controller

 

Warning(16735): Verilog HDL warning at intel_pcie_dma_hwtcl.sv(329): actual bit length 174 differs from formal bit length 160 for port "desc_rdata_o"

Warning(16735): Verilog HDL warning at inigo_pcie_intel_pcie_dma_0.v(64): actual bit length 32 differs from formal bit length 174 for port "dma_wrdm_tx_data_i"

 

I am getting these kind of warning while synthesis

mainly its because of IP parameterization of PCIe DMA 

 

here VFNUM address width

         PFNUM address width

         STATUS_DATA_WIDTH

         STATUS_DATA_WIDHT

how can i fill these columns ? 

anyone please explain with example

 

Thanks 

 

 

0 Kudos
4 Replies
SengKok_L_Intel
Moderator
393 Views

Hi,


These warnings are come with the example design, and we have reported it to our engineering team. For this moment, you may safety ignore it, and we will improve it in the future version.


Regards -SK


10
Beginner
389 Views

Hi 

thanks for reply.

I need to get utilization report of the design. 

because of this these kind of warnings 2lacs registers are removed due to lost fan out.

How can i resolve this?

 

thanks in advance

SengKok_L_Intel
Moderator
378 Views

Hi,


I have generated an example design by using v20.3, and also observed quite a number of "lost fan out" from the IP or DMA controller. Since this happens within the internal IP logic, and those logic might be reserved or not actually using, therefore, there is no way for us to eliminate it. You can just safety ignore it as we don't expect it will impact the IP hardware functionality.


Regards -SK


SengKok_L_Intel
Moderator
347 Views

If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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