Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17268 Discussions

Interfacing with I2C (EEPROM) chip.

Altera_Forum
Honored Contributor II
1,525 Views

Dear all, 

 

I am using Altera Stratix II board.I need to implement I2C interface. 

I have connected the I2C (AT24C04 EEPROM) to the board using 2 pins namly sda and scl. 

 

 

Now My Problem is : 

 

say for write operation ,I need to send device address , word address and data , three things. 

I am showing the code below for that. 

 

 

input clk_50; 

 

inout scl ; 

inout sda ; 

output int_ack_device ,int_ack_word ,int_ack_data; 

 

reg int_ack_device ,int_ack_word ,int_ack_data,exit_flag;  

 

reg [7:0] clk_count ; //used to generate i2c clock scl 

reg out_scl_s1,out_scl_s2,out_scl_s3,out_scl_s4;  

reg [7:0] device_address ; 

reg [7:0] word_address ; 

reg [7:0] data ;  

reg [5:0] state ;//making state = 1 to enter into the state machine .  

reg out_sda ; 

 

 

OPNDRN SDA1 (.in(out_sda ), .out(sda)); 

assign scl = out_scl_s4 ;  

 

//module to derive out_scl_s4 from clk_50. 

always @( out_scl_s4)  

begin 

 

if ((exit_flag == 0))  

begin 

case(state)  

6'b000001: //generating start condition. state 1  

begin 

# 7500 out_sda <= 1'b0 ; 

state <= 6'b000010 ;  

end 

6'b000010: //putting device address on bus  

begin 

out_sda <= device_address[7]; //1  

state <= 6'b000011; 

end 

6'b000011: 

begin 

out_sda <= device_address[6]; //0 

state <= 6'b000100; 

end 

6'b000100: 

begin 

out_sda <= device_address[5]; //1  

state <= 6'b000101; 

end 

6'b000101: 

begin 

out_sda <= device_address[4]; //0 

state <= 6'b000110; 

end 

6'b000110: 

begin 

out_sda <= device_address[3]; //0 

state <= 6'b000111; 

end 

6'b000111: 

begin 

out_sda <= device_address[2]; //0 

state <= 6'b001000; 

end 

6'b001000: 

begin 

out_sda <= device_address[1]; //0 

state <= 6'b001001; 

end  

6'b001001: // putting read/write (R/!W) bit on sda  

begin 

out_sda <= device_address[0]; //0 w 

state <= 6'b001010 ; 

end 

6'b001010: // value on out_sda should come from i2c device. 

begin 

int_ack_device <= out_sda ; //0  

state <= 6'b001011 ; 

end 

6'b001011: 

begin  

out_sda <= word_address[7]; // 1 //this bit is set to one.  

state <= 6'b001100 ; 

end 

 

First ack which i am receiving in int_ack_device is proper.My problem is that when in state 6'b001011: I apply 1 to out_sda.it doesnt go high at all .I am using signaltap tool for seeing the signal. 

I think problem lies in holding scl line by slave.  

Relevant warnings are : 

Warning: Following 4 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results 

Info: Pin int_ack_device has GND driving its datain port 

Info: Pin int_ack_word has GND driving its datain port 

Info: Pin int_ack_data has GND driving its datain port 

Info: Pin sda has GND driving its datain port /* how to remove this warning ??? */ 

 

 

I am seeking for help in this regard.please help. 

 

 

 

-Thanks & Regards  

Tushar
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
810 Views

opencores and niosforum have i2c cores usable with sopc builder.

0 Kudos
Reply