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16009 Discussions

Internal Error : Expected to get 1 pll but found 3 plls for group EMIF_0_mem_ctrl_alt

Honored Contributor II

My design contains several PLL's :  

- a PLL to generate the main system clock. 

- a PLL for the DDR controller. 

- a PLL in a PCIe interface IP. 


Recently my builds have been crashing with an internal error :  

Problem Details 


Internal Error: Sub-system: EMIF, File: /quartus/periph/emif/emif_gen6_emif_system.cpp, Line: 2645 

Expected to get 1 pll but found 3 plls for group EMIF_0_mem_ctrl_altera_emif_170_wp4gjuy 


After I do Project->Clean project, the build succeeds. 


PLL Usage Summary in the .fit.rpt lists : 




DDR_NODE: DDR_NODE_inst_0|mem_ctrl:mem_ctrl|mem_ctrl_altera_emif_161_x274mry:emif_0|mem_ctrl_altera_emif_arch_nf_161_bkdrrci:arch|mem_ctrl_altera_emif_arch_nf_161_bkdrrci_top:arch_inst|altera_emif_arch_nf_pll: pll_inst|pll_inst~_Duplicate_1 

DDR_NODE: DDR_NODE_inst_0|mem_ctrl:mem_ctrl|mem_ctrl_altera_emif_161_x274mry:emif_0|mem_ctrl_altera_emif_arch_nf_161_bkdrrci:arch|mem_ctrl_altera_emif_arch_nf_161_bkdrrci_top:arch_inst|altera_emif_arch_nf_pll: pll_inst|pll_inst~_Duplicate 

DDR_NODE: DDR_NODE_inst_0|mem_ctrl:mem_ctrl|mem_ctrl_altera_emif_161_x274mry:emif_0|mem_ctrl_altera_emif_arch_nf_161_bkdrrci:arch|mem_ctrl_altera_emif_arch_nf_161_bkdrrci_top:arch_inst|altera_emif_arch_nf_pll: pll_inst|pll_inst 


PCIE_XL_INTERFACE:PCIE_TREETOP|xillybus:xillybus_ins|pcie_a10_8x: pcie|pcie_reconfig: pcie_reconfig|pcie_reconfig_altera_pcie_a10_hip_161_5uv7uhy: pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|fpll_g1g2xn:g_pll.g_pll_g12n.fpll_g1g2xn|altera_xcvr_fpll_a10:fpll_g1g2xn|fpll_inst 



Whats up with the the duplicate PLL's? 

Do they cause the internal error? 


The target device is Arria 10/10AX115N3F45E2SG  

I currently use Quartus 17.02, but the same error occurred in 16.1.2 and 16.0.2. 


Full error report : 

Problem Details 


Internal Error: Sub-system: EMIF, File: /quartus/periph/emif/emif_gen6_emif_system.cpp, Line: 2645 

Expected to get 1 pll but found 3 plls for group EMIF_0_mem_ctrl_altera_emif_170_wp4gjuy 

Stack Trace: 

0xaccff: EMIF_GEN6_EMIF_SYSTEM::create_emif_phylite_group_cell() + 0x481 (periph_emif) 

0xb3b8b: EMIF_GEN6_EMIF_SYSTEM::create_emif_cells(CDB_ATOM_NODE*, std::unordered_map<unsigned int, CDB_ATOM_NODE*, STL_HASH_FUNCTOR<unsigned int>, std::equal_to<unsigned int>, std::allocator<std:: pair<unsigned int const, CDB_ATOM_NODE*> > >&) + 0x1ab (periph_emif) 

0x833c1: EMIF_GEN6::create_design() + 0x107 (periph_emif) 

0x68496: PCC_ENV_IMPL:: perform_op(PCC_ENV::OP) + 0x1f6 (periph_pcc) 

0x695a5: PCC_ENV_IMPL::create_design() + 0x1b5 (periph_pcc) 

0x698ea: PCC_ENV_IMPL::refresh_design_until_converged(bool) + 0x18a (periph_pcc) 

0x69ac1: PCC_ENV_IMPL::refresh(PCC_ENV::CONTEXT, std::string const&, bool, bool) + 0xd1 (periph_pcc) 

0x6a485: PCC_ENV_IMPL::load_design() + 0x105 (periph_pcc) 

0x955a1: pcc_load_periph_design + 0x71 (periph_pcc) 

0x51ec7: TclNRRunCallbacks + 0x47 (tcl8.6) 

0x40131: pcc_load_periph_placer + 0x102 (periph_pcc) 

0x51ec7: TclNRRunCallbacks + 0x47 (tcl8.6) 

0x536e7: TclEvalEx + 0x947 (tcl8.6) 

0x539d6: Tcl_EvalEx + 0x16 (tcl8.6) 

0x539fd: Tcl_Eval + 0x1d (tcl8.6) 

0x1aeb5: atcl_tcl_eval(Tcl_Interp*, std::string const&) + 0x12d (ccl_atcl) 

0x34c49: atcl_run_internal_tcl_cmd(Tcl_Interp*, std::string const&, bool) + 0x59 (ccl_atcl) 

0x2354c: fit2_fit_plan_init + 0x23c (comp_fit2) 

0x51ec7: TclNRRunCallbacks + 0x47 (tcl8.6) 

0x13086: fit2_fit_plan + 0x2ec (comp_fit2) 

0x51ec7: TclNRRunCallbacks + 0x47 (tcl8.6) 

0x536e7: TclEvalEx + 0x947 (tcl8.6) 

0xfb366: Tcl_FSEvalFileEx + 0x266 (tcl8.6) 

0xfb47e: Tcl_EvalFile + 0x2e (tcl8.6) 

0x11ebc: qexe_evaluate_tcl_script(std::string const&) + 0x382 (comp_qexe) 

0x18dcf: qexe_do_tcl(QEXE_FRAMEWORK*, std::string const&, std::string const&, std::list<std::string, std::allocator<std::string> > const&, bool, bool) + 0x597 (comp_qexe) 

0x19d7b: qexe_run_tcl_option(QEXE_FRAMEWORK*, char const*, std::list<std::string, std::allocator<std::string> >*, bool) + 0x57e (comp_qexe) 

0x3e06a: qcu_run_tcl_option(QCU_FRAMEWORK*, char const*, std::list<std::string, std::allocator<std::string> >*, bool) + 0x1065 (comp_qcu) 

0x1c586: qexe_standard_main(QEXE_FRAMEWORK*, QEXE_OPTION_DEFINITION const**, int, char const**) + 0x6b3 (comp_qexe) 

0x3b75: qfit2_main(int, char const**) + 0xc5 (quartus_fit) 

0x40720: msg_main_thread(void*) + 0x10 (ccl_msg) 

0x602c: thr_final_wrapper + 0xc (ccl_thr) 

0x407df: msg_thread_wrapper(void* (*)(void*), void*) + 0x62 (ccl_msg) 

0xa559: mem_thread_wrapper(void* (*)(void*), void*) + 0x99 (ccl_mem) 

0x8f92: err_thread_wrapper(void* (*)(void*), void*) + 0x27 (ccl_err) 

0x63f2: thr_thread_wrapper + 0x15 (ccl_thr) 

0x427e2: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0xa3 (ccl_msg) 

0x1ed1d: __libc_start_main + 0xfd ( 










Executable: quartus 





System Information 

Platform: linux64 

OS name: CentOS release 

OS version: 6 



Quartus Prime Information 

Address bits: 64 

Version: 17.0.2 

Build: 602 

Edition: Standard Edition
0 Kudos
2 Replies
Honored Contributor II


Probably you have a DDR interface that more than 40bits data width? 

The duplicate PLL is expected because the EMIF use 3 I/O banks. For EMIF once the EMIF is place into the particular bank, it will use that bank I/O PLL to generate clocks for the I/O banks DDR signals. 


you may refer to EMIF handbook 

Arria 10 EMIF Architecture: PHY Clock Tree section 

Arria 10 EMIF Architecture: PLL Reference Clock Networks section 


(This message was posted on behalf of Intel Corporation)
Honored Contributor II

Yes the DDR is 576b wide. 

But, how does that with the match the "After I do Project->Clean project, the build succeeds." ?