Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15047 Discussions

Internal Error: Sub-system: QSYN, File: /quartus/synth/qsyn/qsyn_cmd.cpp, Line: 1803

Altera_Forum
Honored Contributor I
1,616 Views

I am using opencl 16.1 and quartus 16.1 prime lite for the DE1 soc board. 

 

I try to compile the boardtest example in the de1soc examples. and got the following internal error. This may be an example independent issue. 

Any suggestion ? 

 

Thanks 

 

 

 

Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 119 warnings 

Info: Peak virtual memory: 1193 megabytes 

Info: Processing ended: Wed Jan 25 08:56:21 2017 

Info: Elapsed time: 00:03:22 

Info: Total CPU time (on all processors): 00:02:25 

Internal Error: Sub-system: QSYN, File: /quartus/synth/qsyn/qsyn_cmd.cpp, Line: 1803 

Stack Trace: 

0x17d8d: QSYN_FRAMEWORK::initialize_parallel_helper + 0x88d (quartus_map) 

0x13853: QSYN_FRAMEWORK::execute + 0x233 (quartus_map) 

0x11067: qexe_do_grunt + 0xa7 (comp_qexe) 

0x16063: qexe_run + 0x353 (comp_qexe) 

0x16e51: qexe_standard_main + 0xc1 (comp_qexe) 

0x1b06b: qsyn_main + 0x51b (quartus_map) 

0x13328: msg_main_thread + 0x18 (CCL_MSG) 

0x14b0e: msg_thread_wrapper + 0x6e (CCL_MSG) 

0x15b00: mem_thread_wrapper + 0x70 (ccl_mem) 

0x12a11: msg_exe_main + 0xa1 (CCL_MSG) 

0x29862: __tmainCRTStartup + 0x10e (quartus_map) 

0x8363: BaseThreadInitThunk + 0x13 (KERNEL32) 

0x670d0: RtlUserThreadStart + 0x20 (ntdll) 

 

 

End-trace 

 

 

Error (281039): Finished parallel synthesis of 1 partition(s). 1 partitions did not finish parallel synthesis because there were errors 

Error (281040): Partition "system_acl_iface_hps_hps_io_border:border" did not complete synthesis due to errors
0 Kudos
9 Replies
Altera_Forum
Honored Contributor I
247 Views

Are you using 16.1 or 16.1.1? 16.1 has a known issue with OpenCL compilation and all OpenCL compilations fail. You must install the 16.1.1 update for both Quartus and AOCL if you haven't.

Altera_Forum
Honored Contributor I
247 Views

Hello dears,I am encountering the same errors, did you mange to solve this issue?I am using Quartus 17.1 and OpenCL SDK for FPGA 17.1

Altera_Forum
Honored Contributor I
247 Views

Attach your quartus_sh_compile.log.

Altera_Forum
Honored Contributor I
247 Views

 

--- Quote Start ---  

Attach your quartus_sh_compile.log. 

--- Quote End ---  

 

 

the log is in the attachments "quartus_sh_compile.log". 

 

many thanks in advance.
Altera_Forum
Honored Contributor I
247 Views

Compilation seems to be crashing with an internal error; however, the following line in your log seems strange to me: 

 

Info (125068): Revision "top" was previously opened in Quartus II software version 14.1. Created Quartus Prime Default Settings File 

 

What is your target board? Is your BSP compatible with the version of Quartus you are using? 

 

Also, have you tried updating to 17.1.2 (you have to update Quartus and AOC separately)? 

 

Finally, if you have a license for Quartus, it is proffered to use Quartus Prime Standard or Pro, depending on your target board.
Altera_Forum
Honored Contributor I
247 Views

I am trying with c5soc as the target board, since the BSP was installed by default ( I tried on de0_nano_soc after I got the BSP from terasic but the same problem occured). 

 

Since the BSP was already included in the SDK I assumed it's compatible with Quartus & SDK version 17.1. 

 

For the license, I don't have one, since as I understood that the Quartus Lite is free and the SDK didn't ask for a license ( I am targeting Cyclone V board (DE0-Nano SoC)). 

 

However, Now I am updating Quartus and SDK, I will test again and post the log.
Altera_Forum
Honored Contributor I
247 Views

Hello HRZ, 

 

I updated both AOC and Quartus to 17.1.1 (latest version on website), 

 

I performed the following : 

 

1- trying to compile for board c5soc resulted with the log in the "quartus_sh_compile_c5soc" file in the attachments (same errors). 

2- trying to compile for board de0_nano_soc (using the BSP in the following link: http://mail.terasic.com.tw/~keith/20170703/de0_nano_soc_opencl_bsp.zip (http://mail.terasic.com.tw/~keith/20170703/de0_nano_soc_opencl_bsp.zip)) resulted with different error message (less errors and more progress) as shown in the "quartus_sh_compile_de0_nano" log. 

 

By comparing, the de0_nano progressed more but the error (Error in adjust_plls.tcl!) crashed the whole thing as I understand. 

 

Appreciate your kind help and advice and many thanks for your help.
Altera_Forum
Honored Contributor I
247 Views

If you are using the reference BSPs, then they are compatible with the version of Quartus they are shipped with. I hope updating Quartus solves your problem. 

 

P.S. How much memory do you have on the machine you use for compilation?
Altera_Forum
Honored Contributor I
247 Views

 

--- Quote Start ---  

P.S : Regarding the memory used for compilation, my PC has 4 GB RAM and I'm using it all, it's enough isn't it ? 

--- Quote End ---  

 

 

Actually, this is very likely the source of your problem. Considering the fact that the compilation process is crashing in a different part every time, you are very likely running out of memory. Intel's recommendation for memory size to place and route designs for Cyclone V is 6-8 GB (and probably more if you are using OpenCL): 

 

http://dl.altera.com/requirements/17.1/ 

 

You can easily verify whether you are running out of memory or not by checking your memory and swap usage during placement and routing. I recommend using a machine with at least 8 GB of memory (or preferably, 16).
Reply