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Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/vpr_common/utils

Altera_Forum
Honored Contributor II
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Any ideas why it may happen? 

I just added a PLL to my project based on golden design for Cyclone V SoC devkit. Now, I cannot move forward in compiling the design even when removing PLL instance from top level module. 

 

--Dmitry 

 

Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/vpr_common/utils_profiling.c, Line: 538 

 

Internal Error 

Stack Trace: 

0x119632: vpr_qi_jump_to_exit + 0x58 (fitter_vpr20kmain) 

 

0x43daaf: vpr_final_exit + 0x8 (fitter_vpr20kmain) 

0x4460e2: vpr_exit_at_line + 0x57 (fitter_vpr20kmain) 

0x1d7c58: profile_close_bin + 0x338 (fitter_vpr20kmain) 

0x235dc3: vpr_report + 0x13 (fitter_vpr20kmain) 

0x792f8: VPR_QI_FACADE::vpr_qi_main() + 0x28 (fitter_vpr20kmain) 

0x3d870: fitapi_run_vpr + 0x60 (fitter_fitapi) 

0x3febe: FSV_EXPERT_BASE::place_and_route(bool*) const + 0x16e (fitter_fsv) 

0x444e0: FSV_EXPERT_BASE::invoke_fitter() const + 0x17e0 (fitter_fsv) 

0x3e402: fsv_execute + 0x292 (fitter_fsv) 

0x2cac5: fmain_start(CMP_FACADE*) + 0x565 (fitter_fmain) 

0x1b840: qfit_execute_fit(QCU_FRAMEWORK*, QFIT_FRAMEWORK*) + 0x150 (comp_qfit_legacy_flow) 

0x15afd: QFIT_FRAMEWORK::execute() + 0x2ad (comp_qfit_legacy_flow) 

0x25651: qfit_legacy_flow_run_legacy_fitter_flow + 0x1a1 (comp_qfit_legacy_flow) 

 

0x2e8f6: TclInvokeStringCommand + 0x76 (tcl8.5) 

0x32b1e: TclEvalObjvInternal + 0x2be (tcl8.5) 

0x34310: TclEvalEx + 0x4f0 (tcl8.5) 

0x34d13: TclEvalObjEx + 0x393 (tcl8.5) 

0x3ac31: Tcl_EvalObjCmd + 0x91 (tcl8.5) 

0x32b1e: TclEvalObjvInternal + 0x2be (tcl8.5) 

0x73abf: TclExecuteByteCode + 0x151f (tcl8.5) 

0xb5bc7: TclObjInterpProcCore + 0x107 (tcl8.5) 

0x32b1e: TclEvalObjvInternal + 0x2be (tcl8.5) 

0x73abf: TclExecuteByteCode + 0x151f (tcl8.5) 

0xb5bc7: TclObjInterpProcCore + 0x107 (tcl8.5) 

0x32b1e: TclEvalObjvInternal + 0x2be (tcl8.5) 

0x34310: TclEvalEx + 0x4f0 (tcl8.5) 

 

0x98c70: Tcl_FSEvalFileEx + 0x230 (tcl8.5) 

0x98d6e: Tcl_EvalFile + 0x2e (tcl8.5) 

0xff62: qexe_evaluate_tcl_script(char const*) + 0x43b (comp_qexe) 

0x15515: qexe_do_tcl(QEXE_FRAMEWORK*, char const*, char const*, _Dinkum_std::list<_Dinkum_std::basic_string<char, _Dinkum_std::char_traits<char>, MEM_STL_ALLOCATOR<char> >, MEM_STL_ALLOCATOR<_Dinkum_std::basic_string<char, _Dinkum_std::char_traits<char>, MEM_STL_ALLOCATOR<char> > > > const&, bool, bool) + 0x507 (comp_qexe) 

0x16352: qexe_run_tcl_option(QEXE_FRAMEWORK*, char const*, _Dinkum_std::list<_Dinkum_std::basic_string<char, _Dinkum_std::char_traits<char>, MEM_STL_ALLOCATOR<char> >, MEM_STL_ALLOCATOR<_Dinkum_std::basic_string<char, _Dinkum_std::char_traits<char>, MEM_STL_ALLOCATOR<char> > > >*, bool) + 0x542 (comp_qexe) 

0x32bbe: qcu_run_tcl_option(QCU_FRAMEWORK*, char const*, _Dinkum_std::list<_Dinkum_std::basic_string<char, _Dinkum_std::char_traits<char>, MEM_STL_ALLOCATOR<char> >, MEM_STL_ALLOCATOR<_Dinkum_std::basic_string<char, _Dinkum_std::char_traits<char>, MEM_STL_ALLOCATOR<char> > > >*, bool) + 0x7b1 (comp_qcu) 

0x18b1f: qexe_standard_main(QEXE_FRAMEWORK*, QEXE_OPTION_DEFINITION const**, int, char const**) + 0x641 (comp_qexe) 

0x9517: qfit2_main(int, char const**) + 0xe7 (quartus_fit) 

0x3bb9a: msg_main_thread(void*) + 0x10 (ccl_msg) 

0x75bc: thr_final_wrapper + 0xc (ccl_thr) 

 

0x3c801: msg_thread_wrapper(void* (*)(void*), void*) + 0x5b (ccl_msg) 

0x18bf5: mem_thread_wrapper(void* (*)(void*), void*) + 0xc5 (quartus_fit) 

0xf41d: err_thread_wrapper(void* (*)(void*), void*) + 0x27 (ccl_err) 

0x799c: thr_thread_wrapper + 0x15 (ccl_thr) 

0x4e41d: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0x96 (ccl_msg) 

0x21ec5: __libc_start_main + 0xf5 (c.so.6) 

0x8d69: __gxx_personality_v0 + 0x311 (quartus_fit) 

 

 

End-trace 

 

 

Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
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3 Replies
Altera_Forum
Honored Contributor II
1,219 Views

Hi Dmitry, 

 

Was it possible to see the messages from Quartus prior to the internal error? May be there was a warning or error message that could give a clue about what caused this, sometimes there is.  

 

Regards 

J
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Altera_Forum
Honored Contributor II
1,219 Views

The message itself make no sence for me as device is used for about 10% only. 

 

Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements 

Info (332111): Found 24 clocks 

Info (332111): Period Clock Name 

Info (332111): ======== ============ 

Info (332111): 40.000 altera_reserved_tck 

Info (332111): 20.000 fpga_clk_50 

Info (332111): 1000.000 hps_i2c0_SCL 

Info (332111): 2.500 hps_memory_mem_ck 

Info (332111): 2.500 hps_memory_mem_ck_n 

Info (332111): 2.500 hps_memory_mem_dqs[0]_IN 

Info (332111): 2.500 hps_memory_mem_dqs[0]_OUT 

Info (332111): 2.500 hps_memory_mem_dqs[1]_IN 

Info (332111): 2.500 hps_memory_mem_dqs[1]_OUT 

Info (332111): 2.500 hps_memory_mem_dqs[2]_IN 

Info (332111): 2.500 hps_memory_mem_dqs[2]_OUT 

Info (332111): 2.500 hps_memory_mem_dqs[3]_IN 

Info (332111): 2.500 hps_memory_mem_dqs[3]_OUT 

Info (332111): 2.500 hps_memory_mem_dqs[4]_IN 

Info (332111): 2.500 hps_memory_mem_dqs[4]_OUT 

Info (332111): 2.500 hps_memory_mem_dqs_n[0]_OUT 

Info (332111): 2.500 hps_memory_mem_dqs_n[1]_OUT 

Info (332111): 2.500 hps_memory_mem_dqs_n[2]_OUT 

Info (332111): 2.500 hps_memory_mem_dqs_n[3]_OUT 

Info (332111): 2.500 hps_memory_mem_dqs_n[4]_OUT 

Info (332111): 20.833 hps_usb1_CLK 

Info (332111): 2.500 soc_inst|hps_0|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock 

Info (332111): 2.500 soc_system:soc_inst|soc_system_hps_0:hps_0|soc_system_hps_0_hps_io:hps_io|soc_system_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|afi_clk_write_clk 

Info (332111): 2.500 soc_system:soc_inst|soc_system_hps_0:hps_0|soc_system_hps_0_hps_io:hps_io|soc_system_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk 

Info (332111): Period Clock Name 

Info (332111): ======== ============ 

Info (332111): 40.000 altera_reserved_tck 

Info (332111): 20.000 fpga_clk_50 

Info (332111): 1000.000 hps_i2c0_SCL 

Info (332111): 2.500 hps_memory_mem_ck 

Info (332111): 2.500 hps_memory_mem_ck_n 

Info (332111): 2.500 hps_memory_mem_dqs[0]_IN 

Info (332111): 2.500 hps_memory_mem_dqs[0]_OUT 

Info (332111): 2.500 hps_memory_mem_dqs[1]_IN 

Info (332111): 2.500 hps_memory_mem_dqs[1]_OUT 

Info (332111): 2.500 hps_memory_mem_dqs[2]_IN 

Info (332111): 2.500 hps_memory_mem_dqs[2]_OUT 

Info (332111): 2.500 hps_memory_mem_dqs[3]_IN 

Info (332111): 2.500 hps_memory_mem_dqs[3]_OUT 

Info (332111): 2.500 hps_memory_mem_dqs[4]_IN 

Info (332111): 2.500 hps_memory_mem_dqs[4]_OUT 

Info (332111): 2.500 hps_memory_mem_dqs_n[0]_OUT 

Info (332111): 2.500 hps_memory_mem_dqs_n[1]_OUT 

Info (332111): 2.500 hps_memory_mem_dqs_n[2]_OUT 

Info (332111): 2.500 hps_memory_mem_dqs_n[3]_OUT 

Info (332111): 2.500 hps_memory_mem_dqs_n[4]_OUT 

Info (332111): 20.833 hps_usb1_CLK 

Info (332111): 2.500 soc_inst|hps_0|hps_io|border|hps_sdram_inst|hps_sdram_p0_sampling_clock 

Info (332111): 2.500 soc_system:soc_inst|soc_system_hps_0:hps_0|soc_system_hps_0_hps_io:hps_io|soc_system_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|afi_clk_write_clk 

Info (332111): 2.500 soc_system:soc_inst|soc_system_hps_0:hps_0|soc_system_hps_0_hps_io:hps_io|soc_system_hps_0_hps_io_border:border|hps_sdram:hps_sdram_inst|hps_sdram_pll:pll|pll_write_clk_dq_write_clk 

Info (176233): Starting register packing 

Info (176235): Finished register packing 

Extra Info (176218): Packed 24 registers into blocks of type EC 

Extra Info (176218): Packed 24 registers into blocks of type EC 

Info (11798): Fitter preparation operations ending: elapsed time is 00:00:24 

Info (170189): Fitter placement preparation operations beginning 

Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:02 

Info (170191): Fitter placement operations beginning 

Info (170137): Fitter placement was successful 

Info (170192): Fitter placement operations ending: elapsed time is 00:00:05 

Info (170193): Fitter routing operations beginning 

Error (11128): The following signal cannot be routed: soc_system:soc_inst|soc_system_hps_0:hps_0|soc_system_hps_0_fpga_interfaces:fpga_interfaces|h2f_rst_n[0]. The device does not contain the routing resources required to make this connection
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Altera_Forum
Honored Contributor II
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Hi, 

 

Even though the error message may not make sense from a device utilization perspective, it does (hopefully) point you in the right direction. Do you use this reset signal to reset the PLL you added to the design? Would it be possible for you to try another reset strategy in that case? 

 

I see in the initial post that you seem to get the IE even when the PLL is removed. Try to delete all Quartus generated folders in your project directory (db, incremental_db etc) and start the compilation again. 

 

Cheers
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