Intradomain Skew Problem

[LucasMendes]

I am synthesizing my Verilog design into a Ciclone V (5CSXFC6D6F31C6) and trying to increase FMAX. The design is a SOC (top level) with a processor, a dual port data memory (IPcore), a dual port ROM memory and a UART.

I am using the timing closure recommendations to understand where to fix. The top recommendation is about intradomain skew (it says to place source and destination clock on the same global clock resource, always between memory and a register from the processor), but i have already configured the source clock (an input in SOC) as global signal (global clock). I am using a .qsf file for pin assignments, and the clock configuration is as follows:

set_location_assignment PIN_AF14 -to CLK
set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to CLK

Can someone help me with it?

[sstrell]

Are you failing timing somewhere (provide the timing report) or are you just trying to "push the envelope" and get to a certain Fmax?  What does your .sdc file look like?

[LucasMendes]

I am trying to understand where is the critical path of my design to improve it. I believe (I could be wrong) that this issue is most related to the configuration of the tool (Quartus), than the way I created the logic (like the suggestions about long combinational path).

The timing report I attached is from the top failing path (torv32 is the processor, and "dmem" is the dual port RAM memory IP core). If that's not what you are asking, please correct me.

It was my first time using Timing Analyzer, so I used a .sdc file created by Quartus, and it only has these lines:

set_time_format -unit ns -decimal_places 3

create_clock -name {CLK} -period 1.000 -waveform { 0.000 0.500 } [get_ports {CLK}]

set_clock_uncertainty -rise_from [get_clocks {CLK}] -rise_to [get_clocks {CLK}] -setup 0.170
set_clock_uncertainty -rise_from [get_clocks {CLK}] -rise_to [get_clocks {CLK}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {CLK}] -fall_to [get_clocks {CLK}] -setup 0.170
set_clock_uncertainty -rise_from [get_clocks {CLK}] -fall_to [get_clocks {CLK}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {CLK}] -rise_to [get_clocks {CLK}] -setup 0.170
set_clock_uncertainty -fall_from [get_clocks {CLK}] -rise_to [get_clocks {CLK}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {CLK}] -fall_to [get_clocks {CLK}] -setup 0.170
set_clock_uncertainty -fall_from [get_clocks {CLK}] -fall_to [get_clocks {CLK}] -hold 0.060

[sstrell · Accepted solution]

You need a complete .sdc file that defines all clock domains in the design as well as input and output delay constraints in order to fully constrain the design.

Your timing report shows a very long data path delay between the memory and the CPU.  Is this a CPU of your own design?  The data is going through many levels of logic to reach its destination.  If you built this CPU, you may want to add pipelining to the design to break up these long combinational logic paths.

[LucasMendes]

Thank you for your support. I will try to create a more complete .sdc file. Do you know of any references on how to create this type of file?

The CPU is my own design and is already pipelined. I may need to break these long combinational paths, but a more complete timing analysis (with a complete .sdc file) will certainly help me identify the best place to break.

[RichardTanSY_Intel]

Thank you Sstrell for answering.

Additionally, you can checkout the application note on how to create sdc constraint for input/output interface constraints:

https://www.intel.com/content/www/us/en/content-details/653688/an-433-constraining-and-analyzing-source-synchronous-interfaces.html

You may look for timing related training in our FPGA Training webpage:

https://learning.intel.com/developer/pages/128/intelr-fpga-training

e.g.

Understanding Timing Analysis in FPGAs

Best Design Practice for Timing Closure

Constraining Source Synchronous Interface

Quartus Prime Pro Software Timing Analysis - Part 1 to 5

We also have user guide:

https://www.intel.com/content/www/us/en/docs/programmable/683145/21-3/an-584-timing-closure-methodology-for.html

https://www.intel.com/content/www/us/en/docs/programmable/683664/19-3/reduce-logic-levels.html#prf1571169359466__section_hvg_b1x_ljb

https://www.intel.com/content/www/us/en/docs/programmable/683588/17-1/quick-start-tutorial.html

https://www.intel.com/content/www/us/en/docs/programmable/683068/18-1/using-the-timing-analyzer.html

Regards,

Richard Tan

[RichardTanSY_Intel]

As the initial question has been resolved, I will transitioning this thread to community support.

If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.

Thank you and have a great day!

Best Regards,

Richard Tan