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Valued Contributor III
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Introducing delay in output pin

Hi, 

 

I am using Cyclone IV E FPGA in a board. I want to introduce a fixed amount of delay in an output pin. I have instantiated ALTIOBUF component. In the Assignment Editor, I have selected the instance name, and selected the option "Delay from output register to output pin". However I don't see any effect of this. Whatever value I give here, I don't see any difference. Can someone please suggest where I may be going wrong.  

 

Can someone please suggest any better option for introducing a fixed amount of delay. 

 

regards, 

rajesh
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Valued Contributor III
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Hi,  

 

Can you provide more details of your design? Why do you need to implement this delay? By how much you want to delay signal? Why are you using ALTIOBUF? What signal you want to delay? Is it synchronous or asyncronous?  

Maybe you are entereing invalid values? "Delay from output register to output pin" option has only two valid values 0 and 1. See Cyclone IV datasheet Table 1–42 and Table 1–43.
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Valued Contributor III
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Technically, entering IO timing constraints that reflect your board requirements, and then result in delay being added, is the best way to go. I believe the fitter can even pull the register from the IO cell and put it in the fabric to increase the delay. But the biggest benefit of this is if the delay isn't added for whatever reason, you will see a timing failure. 

That being said, IO constraints can be a pain. I've always done this through the Assignment Editor. I don't have CIV up in front of me, but something like Output Delay Chain 1 to the pin. 

Then look in the Fitter Report's Delay Chain Summary to verify.
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Valued Contributor III
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Hi, 

In the PCB, on my data and clock lines I have different trace lengths. I want to correct for this offset. There are 3 data lines and 1 clock line. Each of these traces have different lengths. I want that all these lines should have the same delay when they come out of the board. This is a source synchronous interface.  

regards, 

rajesh 

 

 

 

--- Quote Start ---  

Hi,  

 

Can you provide more details of your design? Why do you need to implement this delay? By how much you want to delay signal? Why are you using ALTIOBUF? What signal you want to delay? Is it synchronous or asyncronous?  

Maybe you are entereing invalid values? "Delay from output register to output pin" option has only two valid values 0 and 1. See Cyclone IV datasheet Table 1–42 and Table 1–43. 

--- Quote End ---  

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Valued Contributor III
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What device, what 's your data rate(line rate on the IO) and what's your IO standard? How much offset are you trying to correct for?

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Valued Contributor III
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The device is EP4CE40F23C6N. The data rate is 480 Mbps. The IO standard is LVDS. I am trying to correct for offsets between 100-500 ps.

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Valued Contributor III
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I would recommend timing constraint. Take a look here: 

http://www.alterawiki.com/wiki/source_synchronous_analysis_with_timequest 

It's really long, but if you look at the Getting Started and then use Case 3 or Case 4 of the Explicit Clock Shift MEthod, you should be able to do it pretty quickly. If the delay chain only has two settings(I don't remember), then you're not going to be able to dial them in exact, and it's up to timing constraints to see where you're at.
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Valued Contributor III
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Dear Rysc, 

 

Thank you very much for your efforts in writing the 2 articles.  

 

My case is different in 2 ways.  

 

1. The constraints we apply will drive Quartus to adjust the clock delay (in PLL) to meet setup/hold at the external register. Firstly, in my design there is one clock which has to align with 3 different data lines (each of which have different board trace lengths).  

 

2. Secondly, I have one more constraint that the clock can vary from 3 MHz to 480 MHz based on user selection. If I use PLL for adjusting the delays, I need to specify the correct clock frequency, which is not possible in my case. In other words, I can't use PLL. 

 

Can you please suggest a way out. 

 

thanks and regards, 

rajesh 

 

 

--- Quote Start ---  

I would recommend timing constraint. Take a look here: 

http://www.alterawiki.com/wiki/source_synchronous_analysis_with_timequest 

It's really long, but if you look at the Getting Started and then use Case 3 or Case 4 of the Explicit Clock Shift MEthod, you should be able to do it pretty quickly. If the delay chain only has two settings(I don't remember), then you're not going to be able to dial them in exact, and it's up to timing constraints to see where you're at. 

--- Quote End ---  

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Valued Contributor III
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Dear Rysc, 

 

Thank you very much for your efforts in writing the 2 articles.  

 

My case is different in 2 ways.  

 

1. The constraints we apply will drive Quartus to adjust the clock delay (in PLL) to meet setup/hold at the external register. Firstly, in my design there is one clock which has to align with 3 different data lines (each of which have different board trace lengths). The clock can be adjusted to match with just one data line. What can I do for the other 2? 

 

2. Secondly, I have one more constraint that the clock can vary from 3 MHz to 480 MHz based on user selection. If I use PLL for adjusting the delays, I need to specify the correct clock frequency, which is not possible in my case. In other words, I can't use PLL. 

 

Can you please suggest a way out. 

 

thanks and regards, 

rajesh
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Valued Contributor III
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It is possible to use the PLL, but you would have to reconfigure it to different frequencies(which then have a range of operation they will lock at, so these need to intersect). This would also require some sort of way to determine the input frequency. It would be a complete pain and I would avoid doing it to. (I have seen it done many, many years ago) 

Are you doing DDR or Single Data Rate? By that is the data 480Mbps or 960Mbps? The former will be tough, the latter will be impossible. Also, are you sending edge-aligned or center-aligned? (If it's SDR, then the beauty is you can do edge or center just by inverting the clock, which is basically free). 

What are the different skews you're trying to match? You have access to the IO delay chain and that's it, which isn't very much and is not PVT calibrated. If it's SDR you can pull the register out of the IO cell and use internal delays. You're not going to get exact delays, but might get close enough. 

I would say timing constraints are required, as they'll analyze across PVT, account for On-Die Variation, etc. You really can't do all this by hand, and it will show you the window you're working with.
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