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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY satUpCount ISPORT(clock, en : IN STD_LOGIC;
flag8 : OUT STD_LOGIC);
END satUpCount;
ARCHITECTURE RTL OF satUpCount IS
SIGNAL sCntVal : INTEGER RANGE 0 TO 15 := 0;
CONSTANT maxVal : NATURAL := 15;
BEGINPROCESS(clock, en)
BEGIN
IF en = '0' THEN
sCntVal <= 0;
ELSIF FALLING_EDGE(clock) AND sCntVal < maxVal THEN
sCntVal <= sCntVal + 1;
ELSE
sCntVal <= sCntVal;
END IF;
IF sCntVal >= 8 THEN
flag8 <= '1';
ELSE
flag8 <= '0';
END IF;
END PROCESS;
END RTL;
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your flag logic is outside clk edge. your sensitivity list does not cover it. your enable may be starts differently.
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--- Quote Start --- your flag logic is outside clk edge. your sensitivity list does not cover it. your enable may be starts differently. --- Quote End --- Yes I know. But why is there discrepancy between simulating VHO and VHDL ? Is there some settings/scripts that will ensure the same behaviour ?
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There are several issues here:
1. You have not really used the proper template for registered logic. 2. Synthesis ignores sensitivity lists, simulation does not. The synthesis is generating flag purely from async logic, whereas in your simulation flag can only change when clock or enable change. To match the two behaviours, you either need to add sCntVal to the sensitivity list (or if you use VHDL 2008 you can use process(all) ) or synchronise all of your code. 3. If you follow standard practice, and proper templates, Modelsim behaviour will always match real hardware.- Mark as New
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--- Quote Start --- There are several issues here: 1. You have not really used the proper template for registered logic. 2. Synthesis ignores sensitivity lists, simulation does not. The synthesis is generating flag purely from async logic, whereas in your simulation flag can only change when clock or enable change. To match the two behaviours, you either need to add sCntVal to the sensitivity list (or if you use VHDL 2008 you can use process(all) ) or synchronise all of your code. 3. If you follow standard practice, and proper templates, Modelsim behaviour will always match real hardware. --- Quote End --- Thank you. Good answer... By templates, you mean those that Altera provide from the quartus text editor ? Are there more templates than those available from the insert template ?
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I mean just general good practice for VHDL logic, usually presented in any decent tutorial - I think altera provides them via the text editor. But stick to this:
process(clk, async_rst) -- no other signals. No async reset needed if you dont need one
begin
if async_rst = '1' then
-- async reset here
elsif rising_edge(clk) then
-- sync logic here, including enables
end if;
-- NOTHING goes here
end process;
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--- Quote Start --- Yes I know. But why is there discrepancy between simulating VHO and VHDL ? Is there some settings/scripts that will ensure the same behaviour ? --- Quote End --- Your description of setup is not quite right. Your first sim is not modelsim but quartus sim. It does not care about sensitivity list apparently. Your second sim is modelsim and cares about sensitivity list. So flag8 is driven only when clk changes.

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