Is RTL Simulation the same as Functional Simulation

[Altera_Forum]

Hello, can anyone tell me if RTL Simulation is the same as Functional Simulation? I ask because I found a setting in Settings>EDA Tool Settings>Simulation>More EDA Netlist Writer Settings where one can choose Generate netlist for functional simulation only. I am using the Stratix V FPGA and Gate Level Simulation is not supported and if I try clicking Gate Level Simulation I get a popup window that says Generate Netlist. But if I select "Generate netlist for functional simulation only" and click on Gate Level it will launch ModelSim and run a simulation but there is no timing information in the simulation waveforms. Also, the sim takes a long time to finish. However if I simply try an RTL sim it is done very quickly.  

 Thanks, joe

[Altera_Forum]

Recalling the experience with the integrated simulator of older QII editions the functional simulation missed all timing effects and did just "straight forwared" simulation of logic combination while timing simulation includes the internal device delays according to the chip and the routing.  

This does not explain the difference between RTL and functional - I would have expected both to be the same... The difference may be, that RTL is the most "top level" logic implementation while functional at least includes the implementation structure in the chip... Thus an RTL representation of a 8 signal input "AND" function is just the "AND" function, while the chip implementation requires this 8-AND to be generated of the given LUT by cascading, thus ending up in a lot more logic functions to be evaluated when simulating... Nevertheless both ways should give (for pure functional) same result as possible timing issues are not taken care of  Just my two cents, Carlhermann

[Altera_Forum]

RTL simulation is simply a simulation of the source code - no compilation takes place. Hence why it is much faster. It is preferable to do as much simulation and debugging as you can at the RTL level (and it should be possible to do at least 95% of it here, if not all of it with good testbenches).

[Altera_Forum]

RTL simulation is simply a simulation of the source code - no compilation takes place. Hence why it is much faster. It is preferable to do as much simulation and debugging as you can at the RTL level (and it should be possible to do at least 95% of it here, if not all of it with good testbenches).

[Altera_Forum]

From Altera: 

The RTL simulation is just the functional simulation of RTL codes.The RTL simulation is using the VHDL, Verilog HDL or system Verilog design source codes files.     The gate level timing simulation allows you to simulate your design with post-fit timing information. The gate level timing simulation require quartus II generated post-fit timing output netlist file (vho/vo) file and standard delay output file (sdo). The gate level timing simulation is to ensure that the FPGA device’s functionality is correct and meets the entire timing requirement after fitter (place & route flow) in Quartus II software. But, the gate level timing simulation of entire design can be very slow and usually should be avoided. Thus, the gate level timing simulation is not supported for Arria V, Cyclone V, or Stratix V devices. Thus, you are not able to run gate level timing simulation from Quartus II software.     Check page 1-2 of the following link for this information:  http://www.altera.com/literature/hb/qts/qts_qii53025.pdf     For timing check, you can use TimeQuest Static timing analysis tool for 28 nm devices.     If you enable the setting "Generate netlist for functional simulation only" and then click the Gate Level Simulation button, it will run ModelSim and then run a gate level functional simulation only. The gate level functional simulation uses post-synthesis (generated after analysis & synthesis) or post-fit functional netlist file (vho/vo generated after fitter) only to run simulation. The SDO output file is NOT generated by Quartus II if you enable “Generate netlist for functional simulation only” option. The SDO file is the file that contain timing delay information that allow you to perform back-annotation for simulation with VHDL simulators that use simulation libraries that are compliant with VITAL version 2.2b and version 3.0 (VITAL 95); back-annotation for simulation in Verilog HDL simulators and ect. Thus, the gate level functional simulation is to check the FPGA device’s functionality is correct after analysis & synthesis or fitter (place & route flow).     In general, the gate level simulation is run after RTL code is synthesized into a gate-level netlist. Since the gate level simulation of an entire design is using netlist file that contain the standard cells, it is expected to be slower than RTL simulation.      I am afraid it is really hard to tell user when to choose to do a gate level Functional Simulation rather than an RLT Simulation. As per my understanding, fewer FPGA designer going gate-level simulation since it takes long time to run gate level functional/timing simulation. Normally, the gate level simulation is done by ASIC designers to avoid re-spins. Most FPGA designers will do RTL simulation to identify the functional/RTL codes problem since RLT simulation is faster and user can also see all the internal nodes without seeing bad names signals. For gate level signals, some internal nodes will probably rename or removed during optimization. So you can’t trust the internal node's result . The only signals that are surely survived and trusted are at the external ports.     Typically, FPGA designers will also do Static Timing Analysis via timequest by constraining their design correctly and ensure their design pass multicorner timing analysis. After verifying the RTL simulation and timing analysis, the last thing is to use signaltap II tool to verify the behavior on hardware.