We developed a custom IP block which includes own vhdl code, quartus IP blocks and so on. The whole project on its own is a standalone version, meaning that it already has functionality without adding additional logic. It currently runs on a Cyclone V GX.
Since we're using this project in addition to other projects it would be nice to be able to precombile it. Since this project contains time-critical paths we don't want to recompile it every time it has been added to an other project. In our experience, the more occupied the area in the FPGA is the more likely are timing issues. In the end, we don't want the custom IP project to be affected by this time-area tradeoff.
It would be nice if you might throw me some keywords or strategies to avoid the above described issue.
Set up a Logic Lock region for the IP to lock it to the area of the device where it is located and then use incremental compilation, setting the design as a design partition, to export the design as a .qxp file. You can then use that .qxp as a design file in any other project.
Yes i agree sstrell, we can generate QXP file and use it in our design.
Few points to consider.
- Parameterization is not possible after creating QXP .
- Also use of post-fit netlist while creating an QXP will restrict the placement and routing in targeted device.
- QXP files can be used within an entire device family.