Hi all.I have a question about $writememb command in Verilog coding. I can run $readmemb command without problem, but I can't get any output from $writememb command. I have my code compilation passed without error, but the target file doesn't get anything written in it after run. There are very few references on google and I am rather confused whether $writememb is a valid command in Quartus II. If it is, can anyone share the experience on how to use the command correctly? Thanks.
$readmemb() works in a verilog initial block to set the initial contents of a block ram. This is valid in QuartusII to fill a register array (eg, block rams) with data at FPGA configuration time. It will work either in QuartusII (implementation) or modelsim (simulation).However, $writememb() makes no sense in an FPGA implementation itself. Write the memory contents where? $writememb() would only be valid and useful in a test bench, not the FPGA itself. It does work in modelsim (simulation) as in a test bench context.