Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
15672 Discussions

Is my IP integration of modular-sgdma (with prefetcher enabled )is correct ?


i enabled prefetcher core option enabled. where should i connect this additional ports descriptor read master and write master. ? and anyone help me with the concept how and where descriptors should kept ready and how to move them once. and how to start servicing of each descriptor and all ? please look into the attachment and check whether integration is even correct at first place ?? this is on S10 board.


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I see some mistakes :

1- where is the clock source

2-Connect the NIOS II Instruction master to the memory that will hold the code only, the rest should be connected to the data master.

3- Where is the descriptor memory? I cannot see it.

4-What errors the Qsys shows?


Thanks for ths answer. The picture shown is somepart only. There was a clock source and reset source. We use 4 memories i.e onchip memories. One for holding elf file i.e code memory and other for storing descriptors. Other as source buffer, and other as destination buffer. We fill data in source buffer from nios via small "for loop". Now the question is , want a C code to examine this msgdma performance while moving data into destination buffer i.e onchip mem 4.

Reviewed pdf files, HAL api drivers , internet search ..etc,​ even webcase not solved this issue till now.