Is there a way to get a testbench onto an FPGA? Need to generate an output pulse.

[thef5]

`timescale 1 ps/ 1 ps   module tb_pulse(); // constants // general purpose registers reg FIRE; reg MOSI; reg SCLK; reg SS; // wires wire pin_name5; wire pin_name6; wire pin_name7; wire pin_name8;   // assign statements (if any) pulse i1 ( // port map - connection between master ports and signals/registers .FIRE(FIRE), .MOSI(MOSI), .pin_name5(pin_name5), .pin_name6(pin_name6), .pin_name7(pin_name7), .pin_name8(pin_name8), .SCLK(SCLK), .SS(SS) ); initial begin #30000 $stop; end   // FIRE initial begin FIRE = 1'b0; FIRE = #19000 1'b1; FIRE = #1000 1'b0; end   // MOSI initial begin MOSI = 1'b0; MOSI = #4500 1'b1; MOSI = #1000 1'b0; MOSI = #2000 1'b1; MOSI = #1000 1'b0; end   // SCLK initial begin SCLK = 1'b0; SCLK = #500 1'b1; SCLK = #500 1'b0; SCLK = #500 1'b1; SCLK = #500 1'b0; SCLK = #500 1'b1; SCLK = #500 1'b0; SCLK = #500 1'b1; SCLK = #500 1'b0; SCLK = #500 1'b1; SCLK = #500 1'b0; SCLK = #500 1'b1; SCLK = #500 1'b0; SCLK = #500 1'b1; SCLK = #500 1'b0; SCLK = #500 1'b1; SCLK = #500 1'b0; SCLK = #500 1'b1; SCLK = #500 1'b0; SCLK = #500 1'b1; SCLK = #500 1'b0; SCLK = #500 1'b1; SCLK = #500 1'b0; SCLK = #500 1'b1; SCLK = #500 1'b0; SCLK = #500 1'b1; SCLK = #500 1'b0; SCLK = #500 1'b1; SCLK = #500 1'b0; SCLK = #500 1'b1; SCLK = #500 1'b0; SCLK = #500 1'b1; SCLK = #500 1'b0; SCLK = #500 1'b1; SCLK = #500 1'b0; SCLK = #500 1'b1; SCLK = #500 1'b0; SCLK = #500 1'b1; SCLK = #500 1'b0; SCLK = #500 1'b1; SCLK = #500 1'b0; end   // SS initial begin SS = 1'b1; SS = #1000 1'b0; SS = #16000 1'b1; end endmodule  

I have this as my top-level entity and I get an error saying, "Can't synthesis current design -- Top partition does not contain any logic."