Is there a way to use design level names with 'get_pins' when creating constraints?

[Altera_Forum]

Hello, 

 I am trying to create timing constraints for my design in an SDC, but am having trouble getting 'get_pins' to filter the correct nodes. By that I mean, it won't find any because the names change so significantly during the compilation.  Some, for example those to/from the PLL, are simple to find with Name Finder in TimeQuest, but for others I've had to use the RTL Netlist viewer to track the path of the clock to get the correct pin names. An example is below. I created a divider in VHDL and instantiated it as ClockDivider with two pins. This was compiled into three components and each of these has a number of pins and by the time I am in Name Finder I am not even sure which one is 'correct' (e.g. if my divider is creating a clock, do I want the data [combout] of Equal0 or [outclk]?)  https://www.alteraforum.com/forum/attachment.php?attachmentid=7267   Is there any way to configure Quartus so I can use the names at the 'design level' in my filters (e.g. [*clockdividier|ClkOut])? Unless the net is removed entirely (which would only happen if it wasn't connected to anything, correct?) surely there is some map between these names and the nets post-compilation?  Or is there some proper way to create the constraints that I am missing and am just making it hard for myself? It's just I can't imagine this method working for big designs with hundreds of constraints, or those worked on by multiple people that change often, so there must be a better one.

[Altera_Forum]

I almost never use [get_pins..], part of which is for the reasons you describe above. Use get_keepers or get_registers(same thing in this case) and use the name of the register. 

create_generated_clock -name ripple_clk -source [get_ports clkin] [get_keepers {ClockDivider:clockdivider|Counter[10]}] -divide_by 1024 (I made this up, so adjust accordingly). The only time I use get_pins is to grab the pins on a PLL, i.e. if this clock divider was driven by a PLL then the -source option would be [get_pins PLL_name], which I would get the syntax from derive_pll_clocks. THe other place I use it is on a clock mux which is combinatorial. I put a (* keep *) attribute on the output and use the |combout name for the get_pins assignment.

[Altera_Forum]

This thread has some discussions about using TimeQuest for accessing nodes within the design; 

 http://www.alteraforum.com/forum/showthread.php?t=39233  I also found that the RTL netlist API was able to view nodes that were not present in the SDC netlist. However, adding 'keep' synthesis constraints to the design preserved some nodes in the SDC netlist.  Perhaps that thread will provide some ideas.  Cheers, Dave

[Altera_Forum]

Rsyc, Dave, Thank you both for replying. Those tips and that link are useful and with a better understanding I am getting some constraints in now!