Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Is there a way to verify Pins Assignment (Location, IO Standard, etc) before running the Full Flow (Synthesis, Fitter, etc)?

ldm_as
Novice
240 Views

Hi All,

 

Is there a way to verify Pins Assignment (Location, IO Standard, etc) before running the Full Flow (Synthesis, Fitter, etc)?

 

Thank you!

 

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1 Reply
MEIYAN_L_Intel
Employee
100 Views

Hi,

 

There is a way to validate the pin assignment against predefined I/O rules for target device. in Chapter 3.4 as the link below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-design-constraint...

 

Thanks

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