Is there any openCL example that uses above 70% DSP resource usage?

[3f28dsboek]

Does anyone know an example of an openCL fpga that uses 70%+ DSP resources?

On stratix 10 is the best 

Or any RTL example that uses 70%+ DSP resources of stratix 10? 

Thanks a lot

[BoonBengT_Intel · Accepted solution]

Hi @3f28dsboek,

Thank you for posting in Intel community forum, hope all is well and apologies for the delayed in response.
Following up on the queries, please do let us know if the doubts/clarification are still open, and we would try our best to clarify.

Best Wishes
BB

[BoonBengT_Intel]

Hi,

Greetings, there is no further clarification. Hence thread will no longer be monitored. For new queries, please feel free to open a new thread and we will be right with you. Pleasure having you here.

Best Wishes
BB