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Is waitrequestAllowance suported for Altera EMIF external mem interface?

FPGAOLOG
New Contributor I
523 Views

The Avalon document mentions waitrequestAllowance parameter but I cant see a way to set it in either Avalon mm bridge or EMIF Avalon interfaces.

How can I set it to 1 for EMIF Avalon interface?

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1 Solution
FPGAOLOG
New Contributor I
248 Views

" waitrequest will usually only be ...". There is no usually in RTL. There is always. So waitrequest may be asserted DURING the burst. This means everything connected to waitrequest must be combinatorial, and can't be pipelined.

 

Thanks for the help. You may close this ticket.

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11 Replies
sstrell
Honored Contributor III
466 Views

Interface properties like that are usually for when you create a custom component that makes use of that property.  It may or may not be available as a parameter for an off-the-shelf IP.  If it's not in the parameter editor, it's not available for customization.

What are you trying to accomplish?  Perhaps there's an alternate way to do it.

FPGAOLOG
New Contributor I
434 Views

I am trying to avoid combinatorial waitrequest signal  handshaking between the ddr IP and the user logic .

sstrell
Honored Contributor III
426 Views

If you're using Platform Designer, you don't really have a choice in the matter. waitrequest is a required signal for the Avalon standard and required by PD on the host side.

If you are instantiating the EMIF directly in your Quartus project, it does not need to have the Avalon wrapper.  

Did you try creating an example design from the EMIF parameter editor to see what this type of connection between user logic and the controller can look like?

AdzimZM_Intel
Employee
405 Views

Hello,


May I know if your question has been answered?


Regards,

Adzim


FPGAOLOG
New Contributor I
391 Views

No it is not.

I said " avoid combinatorial waitrequest", not "avoid waitrequest".

But I did dig in to the code and found out waitrequestAllowance is not supported by Intel EMIF interface claiming it has Avalon interface but not complying on this setting.

Please read the definition of waitrequestAllowance and why it is needed for before answering .

AdzimZM_Intel
Employee
384 Views

Hi,


Maybe you can share the issue that you're facing why simulating the design?


Thank you.

Adzim


FPGAOLOG
New Contributor I
378 Views

I need tis at the EMIF user interface:

FPGAOLOG_0-1647358971725.png

 

 

instead of this:

 

FPGAOLOG_1-1647359043418.png

Avalon® Interface Specifications
Updated for Intel® Quartus® Prime Design Suite: 20.1

 

https://d2pgu9s4sfmw1s.cloudfront.net/DITA-technical-publications/PROD/PSG/mnl_avalon_spec-683091-66...

AdzimZM_Intel
Employee
314 Views

Alright, I understand on what you're trying to do.

But the waitrequestAllowance signal is the internal setting hardcoded in EMIF IP that shouldn't be touched by user.

Changing this signal might cause functionality failure in the EMIF IP.


Have you tried the burst operation?



If you want to optimize the controller performance, you can refer to EMIF User Guide for the device that you used.





FPGAOLOG
New Contributor I
305 Views

I did not ask for touching internal settings of EMIF. I asked if EMIF supports waitrequestAllowance parameter for the user. And I found out looking into EMIF code that the answer is no. There is no such thing in the code but instead a ready signal is inverted to create the waitrequest signal.

 

I am already using burst operation. But there is no explanation for waitrequest will not be asserted during burst. Can you tell that When burst start, waitrequest will not be asserted until the end of the burst?

sstrell
Honored Contributor III
261 Views

waitrequest back to your user logic is handled by a combination of the signal coming from the agent (the EMIF IP) and the interconnect (usually for arbitration purposes but any time the agent can't currently accept a command).

If you initiate a burst and then waitrequest to your user logic goes high, that means your logic (host) gets access to the agent until the burst completes.  As the Avalon spec shows (figure 14 and 15 in the latest version of the doc), for a burst, waitrequest will usually only be asserted at the beginning of the burst or whenever the interconnect (or agent) requires the host to continue asserting the control signals for some reason (typically arbitration).

I think this is why Adzim suggested using bursts, since waitrequest isn't held high throughout them.

FPGAOLOG
New Contributor I
249 Views

" waitrequest will usually only be ...". There is no usually in RTL. There is always. So waitrequest may be asserted DURING the burst. This means everything connected to waitrequest must be combinatorial, and can't be pipelined.

 

Thanks for the help. You may close this ticket.

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