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Is waveform generation disabled in Questa FSE?

New Contributor I

I'm not able to generate waveform files (VCD or WLF) when running Questa FSE  using vlog/vsim under Linux.

The script used to work when running Modelsim ASE.

The exact same Verilog source will generate a VCD file when running a different simulator.  It's simply doing initial $dumpvars; Using Questa FSE vsim the  simulation is running as expected but the resulting VCD have no data in the $dumpvars section.


When I pass a do file to vsim with the following content:

log -r /*
run 10000ms;
quit -f

I get the following error:

# ** UI-Msg: (vish-4014) No objects found matching '/*'.

Did the commands change or has this feature been deliberately disabled in Questa FSE?

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4 Replies

Hi zener,


I found a similar case here: 


Looks like the error occurred due to "do script" is exiting early because you tried to log all signals into a wlf file using the command log -r /*.


Best regards,

New Contributor I

Thank you for the feedback. But the post does not answer the actual problem where it's stated:
But no idea how to resolve the problem with no objects being included in the wlf.

The problem is twofold:

1) Why can't I add all the signals to the wlf file?
I removed the log statement and the simulation is running (what I did to generate the vcd file previously)
The simulation is running and the clock is running so there are signals toggling in the simulation.
Why does it not add any signals when I do log -r /*
I even tries log -r * and add wave -recursive * without any luck. This is what I've done in modelsim_ase in the past.
What is the Questa syntax to add all signals in the simulation to the wlf dump file and what arguments have to be added to the vsim command line?

2) Why is the data section of the vcd file empty when I run initial $dumpvars; ?
If I run the exact verilog source in the Vivado simulator (xelab and xsim) I see the signals toggle in the $dumpvars section of the vcd file.
Are any special command line arguments required to xsim to make sure that all signals are added to the vcd file specified in the verilog source?

New Contributor I

The answer to my problem is that the vsim option " -voptargs=+acc" has to be added to the command line. It will solve both cases above.


Hi zener,


I see. " -voptargs=+acc" is needed to preserve visibility of all objects in the design.


Btw, thanks for your answer and post. They helps a lot.


I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Best regards,