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jrrguzman
New Contributor I
590 Views

Issue when manually instantiating clock buffers in Arria 10

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Hi,

 

I'm using a signal which is used in the design as logic and as clock (at separate locations).

 

If I just run the design flow, Quartus (Prime Standard 17.0) is able to instantiate a clock buffer (CLKCTRL element) at the right place. However if I try to instantiate the clock buffer myself within the code (so I can define the clock in the global constraints file), the fitter tells me that it can't find a proper location for the buffer...

 

Is there something fundamentally wrong if I try to instantiate the buffer manually or is it another Quartus bug? It's quite frustrating because I think I am essentially doing the same as the Fitter does by itself.

 

Cheers

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1 Solution
jrrguzman
New Contributor I
50 Views

Hi all,

 

I figured out the issue: The signal that I'm trying to buffer comes from a LVDS input and I do not instantiate the differential input buffer manually. At this point if I run the fitter-placement, it seems the clock buffer is placed before the inferred differential input buffer and it makes the fitter fail miserably because it can't find the signal, although synthesis has already inferred the LVDS input buffer. (@GNg​ Maybe something you should consider fixing for next Quartus releases).

 

To work-around that, I had to manually instantiate the differential input buffer ussing the ALTERA primitive: ALT_INBUF_DIFF. With that in place Quartus does not complain and gets me a clean implementation.

 

Cheers

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3 Replies
sstrell
Honored Contributor II
50 Views

How are you instantiating and connecting the clock control block to the rest of your design? Is it fed directly by an external clock or an internal signal in your design? If you show the code that may help. There must be some conflict. Can you also post the error messages the Fitter is giving you?

 

#iwork4intel

GuaBin_N_Intel
Employee
50 Views
Which clock network are you choosing, eg global , regional or others https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/n2sw_nii52006.pdf, Table 2-1? Each mode has routing limitation and could give similar error when either your reference clock pin or PLL location could not reach it . Please see https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_handbook.pd..., 4.1.3 ,pg 75
jrrguzman
New Contributor I
51 Views

Hi all,

 

I figured out the issue: The signal that I'm trying to buffer comes from a LVDS input and I do not instantiate the differential input buffer manually. At this point if I run the fitter-placement, it seems the clock buffer is placed before the inferred differential input buffer and it makes the fitter fail miserably because it can't find the signal, although synthesis has already inferred the LVDS input buffer. (@GNg​ Maybe something you should consider fixing for next Quartus releases).

 

To work-around that, I had to manually instantiate the differential input buffer ussing the ALTERA primitive: ALT_INBUF_DIFF. With that in place Quartus does not complain and gets me a clean implementation.

 

Cheers

View solution in original post

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