Issue with Pin assignment using Quartusii

[Altera_Forum]

Hi all, 

  During compiling process of design at I/O analysis stage a critical warning message is coming stating that "No exact pin location assignments for 29 pins of 49 total pins". Please help me to over come this.

[Altera_Forum]

You don't need to multipost your message. 

Why don't you assign pin locations to all your ports? You mention in your other message that you want them to be automatically assigned by Quartus, and I don't understand why.

[Altera_Forum]

In your pin assignment, you are leaving certain pins unassigned, that is why this warning is coming. If, they are of no use, then you can remove them from entity and make them as signals, else you map them to free I/Os. It might happen that if you havent assigned some pins, then they may drive other things on your board, giving rise to erroneous behavior (this might be the reason for warning being critical)

[Altera_Forum]

I didn't assign any pins manually, First I just added my design files to the project and then I tried to compile them using Compile Design located at tasks pane. So when it comes to I/O assignment analysis tool is producing a critical warning message as I said in my previous post.  

When I looked at my QSF, pins are allocated for all my Data pins and there are no pin allocations for Address and other signals(control) but the I/O standards are assigned. That implies tool has allocated the pins for data automatically i.e without my knowledge. I want the similar way for other signals too.   For all Address/control signals the TCL assignment commands in QSF is as follows set_instance_assignment -name io_standard "sstl-2 class ii" -to ddr_a[6] -tag "variation:ddr"  whereas for data and strobe it looks as follows set_location_assignment pin_d28 -to ddr_dq[0] -tag "variation:ddr" set_global_assignment -name assignment_group_member ddr_dqs[1..0] -section_id ddr set_instance_assignment -name io_standard "sstl-2 class ii" -to ddr_dqs[1] -tag "variation:ddr"  So for all Address control signals I need to do the pin allocation manually using pin planner.

[Altera_Forum]

It seems to me, that you're not actually asking about fitter warnings rather than how to assign pins for a DDR memory interface appropriately. You should follow the suggested method in the respective MegaFunction's manual.