Issue with Quartus Prime PRO for Stratix 10 when using a string type in a VHDL project.

[JDlug]

Hello,

When using "Quartus Prime Pro 20.1" software with "Stratix 10" chip, I have a problem with VHDL string type in my projects. At the same time, I don't have this problem when using "Quartus Prime Standard Edition 19.1" with "MAX 10" FPGA. For example, the problem occurs when I compile the following simple VHDL code:

 LIBRARY ieee;

 USE ieee.std_logic_1164.all;

 ENTITY e1 IS

  PORT 

  (

   s_out: OUT string(1 to 2)

  );

 END e1;

 ARCHITECTURE arch1 OF e1 IS

 BEGIN

  s_out <= "ab";

 END arch1;

The compilation process stop suddenly and the error popup window appears with the message: "Sorry! The Quartus Prime software quit unexpectedly". Here is a preview of the report:

………………………………………………………………

Problem Details

Error:

Internal Error: Sub-system: QIS, File: /quartus/synth/qis/qis_name_processor.cpp, Line: 779

\s_out[1].'|' is not a valid node name

Stack Trace:

 Quartus   0xa4d85: QIS_NAME_PROCESSOR_IMPL::create_names + 0x885 (synth_qis)

 Quartus   0x3834b: QIS_RTL_STAGE::IMPL::create_instance_name_for_node + 0x8b (synth_qis)

 Quartus   0x38b0d: QIS_RTL_STAGE::IMPL::create_names_for_all_nodes_post_extraction + 0x2dd (synth_qis)

 Quartus   0x3e9ab: QIS_RTL_STAGE::IMPL::post_process_elaborated_entity + 0xc6b (synth_qis)

 Quartus   0x3a631: QIS_RTL_STAGE::IMPL::elaborate + 0x16d1 (synth_qis)

 Quartus   0x18e2e: qis_elaborate + 0x26e (synth_qis)

 Quartus   0x16442: TclNRRunCallbacks + 0x62 (tcl86)

 Quartus   0x17c4d: TclEvalEx + 0x9ed (tcl86)

 Quartus   0xa6a8b: Tcl_FSEvalFileEx + 0x22b (tcl86)

 Quartus   0xa5136: Tcl_EvalFile + 0x36 (tcl86)

 Quartus   0x156f6: qexe_evaluate_tcl_script + 0x4e6 (comp_qexe)

 Quartus   0x145e3: qexe_do_tcl + 0x4b3 (comp_qexe)

 Quartus   0x1acae: qexe_run_tcl_option + 0x5ee (comp_qexe)

 Quartus   0x18c31: QCU::DETAIL::intialise_qhd_and_run_qexe + 0xa1 (comp_qcu)

 Quartus   0x2b0e2: qcu_run_tcl_option + 0x2f2 (comp_qcu)

 Quartus   0x13cc: qsyn2_tcl_process_default_flow_option + 0x1dc (quartus_syn)

 Quartus   0x1a5b0: qexe_run + 0x460 (comp_qexe)

 Quartus   0x1b6ea: qexe_standard_main + 0x26a (comp_qexe)

 Quartus   0x3039: qsyn2_main + 0x129 (quartus_syn)

 Quartus   0x158d8: msg_main_thread + 0x18 (CCL_MSG)

 Quartus   0x16f81: msg_thread_wrapper + 0x71 (CCL_MSG)

 Quartus   0x21040: mem_thread_wrapper + 0x70 (ccl_mem)

 Quartus   0x14e5d: msg_exe_main + 0x20d (CCL_MSG)

 Quartus   0x4924: __scrt_common_main_seh + 0x11c (quartus_syn)

 Quartus   0x17bd3: BaseThreadInitThunk + 0x13 (KERNEL32)

 Quartus   0x6ce70: RtlUserThreadStart + 0x20 (ntdll)

End-trace

Executable: quartus_syn

Comment:

None

System Information

Platform: windows64

OS name: Windows 10

OS version: 10.0

Quartus Prime Information

Address bits: 64

Version: 20.1.0

Build: 177

Edition: Pro Edition

………………………………………………………………

How can I solve this problem?

Thank you in advance for any help.

(jd)

[KhaiChein_Y_Intel]

Hi,

I have filed a case to our engineering to report this error. I will update once I received the reply from the team.

Thanks.

Best regards,

KhaiY

[JDlug]

Hi, Thank you very much. So I will be waiting for further information hoping for a solution. Thanks again. (jd)

[KhaiChein_Y_Intel]

Hi JD,

I received the feedback from the team. This error is due to not all ASCII characters are readable and we do not support that in Quartus. Internal error will occur when user trying to create a name for that. Is there any reasons why do you want to use characters in your design ? Could you use some other data type to achieve the goal?

Thanks.

Best regards,

KhaiY

[JDlug]

Hi KhaiY,

Thank you for your respons. I am sorry that I did not answer faster, but your reply did not reach my mailbox at all. I just noticed it here.

You wrote:

> This error is due to not all ASCII characters are readable

I am sorry but I don't understand this explanation. It must be some kind of misunderstanding. What does it mean: "not all ASCII characters are readable"? Are we talking about OCR or about VHDL language? An ASCII character is nothing more but one byte (logic vector of eight bits)! You can't read some bits if the type is STRING and you can read them when the type is STD_LOGIC_VECTOR? I am completely lost here. I really don’t get it!

> and we do not support that in Quartus.

Does the Quartus team really say that? The engineers? But it's really not true! I know you do support that in Quartus! How is it possible that they say so? You can check it easily by yourself. The same simple example code I put here before, compiles correctly without any problems in Quartus Prime when you choose the MAX10 chip instead of the Stratix 10. It seems to me that the issue concerns only the "Stratix 10 device support". Did I misunderstand something?

> Internal error will occur when user trying to create a name for that.

I am sorry I don't understand this sentence. English is not my native language. Could you please explain it to me with another words?

> Is there any reasons why do you want to use characters in your design ? 

Yes of course. For some applications, it is much better to use STRING type. I am working on projects where I need to analyze incoming text and create another text responses. In such cases, the use of STRING type makes coding much easier.

> Could you use some other data type to achieve the goal?

Yes, I could but it would be a nightmare for me. I already have a lot of code with STRING type in my projects. It would be months of work to modify everything. The situation is this: I just bought a very expensive evaluation kit containing Intel Stratix 10 FPGA and now I can't use my projects on it! I am depressed. :-( This is now the second problem that I have with Stratix 10 in a short time. Please help me with this and don't tell me you do not support something that is standard for the VHDL language.

Best Regards,

(jd)

[KhaiChein_Y_Intel]

Hi JD,

I conveyed your concern to the team, please see the reply below:

If customer do not want to change their design, the only option for them before we fix the issue, is to turn off state machine inference using the following qsf for the whole design. It may not be desirable though but it will unblock customer from this error. 

set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE OFF

Could you add the above setting in the QSF file?

Thanks.

Best regards,

KhaiY

[JDlug]

Hi, Thank you very much for your answer. It's not that I don't want to change the design. Modifying everything that already works great with other chips will take a long time and is illogical. I did many tests with the "ENABLE_STATE_MACHINE_INFERENCE OFF" assignment you wrote about. It helped with this very simple code that I put here, and the window of the unexpected error message does not appear now, but it did not help in my real projects. :-( I still have another problems. For example, in a certain project without the setting: "set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE OFF" I get: Error(13787): VHDL error at fpga_net.vhd(378): "statement" is not synthesizable since "eth.str_1[7].'�'" does not hold its value under NOT(clock-edge) condition However, when in the same project I put this setting: "set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE OFF" to the .QSF file, the above error disappears but many other errors such as this appear: Error(13076): The node "eth_instance_1|data.str_1[1][4]" has multiple drivers. Error(20073): "non-tri-state driver "eth.str_1[1][4]"" is one of the multiple drivers. Error(20073): "constant GND" is one of the multiple drivers. This is strange, because in my design there is only one place where I set the str_1 variable. I don't really see any reason for these errors in my code. And again, all the above mentioned errors do not show up when building exactly the same project but for MAX10, Cyclone II, Cyclone III or Cyclone IV FPGAs. All my projects with these chips (after a very quick compilation) work perfect and without problems. Problems happen only with Stratix 10. The Quartus Prime shows confusing errors only when I use STRING type, and there are no errors at all when I do not use STRING type. But then, the compilation inexplicably takes a long time. The "ENABLE_STATE_MACHINE_INFERENCE OFF" does not solve the issue. :-( The good news is that you've wrote that there will be a fix for this. Thank you. I understand that this may take some time and I will be patient. If there is anything more I could tell you about my problems with Quartus Prime to help find the bug - let me know. I'll do my best to help. Thank you. (jd)

[KhaiChein_Y_Intel]

Hi JD,

I understand that the "ENABLE_STATE_MACHINE_INFERENCE OFF"

assignment helped in the simple code attached in this forum post. The Internal Error window does not appear in the simple code but this setting did not help in the real projects.

Could you share the file that you see the error after applying the setting?

Thanks.

Best regards,

KhaiY

[JDlug]

Hi KhaiY, These errors appeared in my large project. Give me some time and I'll try to prepare a small example that will show the same mistakes. I'll put it here when I'm ready. Thank you. (jd)

[KhaiChein_Y_Intel]

Hi JD,

Sure.

Thanks.

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi,

Do you have any updates?

Thanks.

Best regards,

KhaiY

[JDlug]

Dear KhaiY, Thank you for your message and for remembering my problem.. but I'm not ready yet. :-( I am very sorry about this delay. I have so many different problems lately. I tried to prepare a code showing the issue but I didn't have enough time. We have the end of the semester here at the university and I have hundreds of students to whom I have to give grades. And because of coronavirus it is a crazy time. I'll prepare the code as soon as possible. As to the issue: Solving this Stratix_10 problem in Quartus Prime Pro is very important to me. In general, I think the problem appears when sharing string data between different entities. I need to prepare a short code showing this problem, but as I told you before, each compilation of the simplest code for Stratix_10 that I try to test takes me at least 9 minutes! which means: only seven tries take about an hour. This is not the case with another family of FPGAs (MAX10, Cyclon_IV and others). I promise that I'll do my best to prepare the code showing the issue as soon as possible. It is important for me because without your help in solving this problem, I can't and I won't be able to use my own IPs codes for the Stratix_10 chips. :-( Best Regards, (jd)

[JDlug]

Hi, Motivated by your message here and your willingness to help, I spent the last night preparing a code showing the problem. I enclose it at the end of this message. The code doesn't make any sense, but it's rather compliant with the VHDL standard and compiles correctly for MAX10 and Cyclone_IV FPGA chips. But when I choose Stratix 10 (and also Cyclone 10, which I discovered yesterday) Quartus Prime shows errors. if there is: set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE ON I get exception error: "Sorry! The Quartus Prime software quit unexpectedly." if there is: set_global_assignment -name ENABLE_STATE_MACHINE_INFERENCE OFF I get processing errors: Error(13076): The node "instance_1|str_1[1][0]" has multiple drivers. Error(20073): "constant GND" is one of the multiple drivers. Error(20073): "non-tri-state driver "str_1[1][0]"" is one of the multiple drivers. Error(13076): The node "instance_1|str_1[1][1]" has multiple drivers. Error(20073): "constant GND" is one of the multiple drivers. Error(20073): "non-tri-state driver "str_1[1][1]"" is one of the multiple drivers. Error(13076): The node "instance_1|str_1[1][2]" has multiple drivers. Error(20073): "constant GND" is one of the multiple drivers. Error(20073): "non-tri-state driver "str_1[1][2]"" is one of the multiple drivers. Error(13076): The node "instance_1|str_1[1][3]" has multiple drivers. Error(20073): "constant GND" is one of the multiple drivers. Error(20073): "non-tri-state driver "str_1[1][3]"" is one of the multiple drivers. Error: Failed to synthesize partition As you can see, the errors say that "str_1" has multiple drivers but there is only one explicit place where "str_1" is driven. The command: str_1:="ABCD";. These errors disappear when you do a tiny change in the code. For example, they dissappear when you comment the line "data<=vec_1(3 downto 0);". It makes no sense to me because this line does nothing with "str_1"! The errors also disappear when you change: if s2/=s1 then s2:=s1; str_1:="ABCD"; end if; to only: str_1:="ABCD"; which is completely strange to me, but I understand that the driver here becomes stronger then. Of course, the errors also disappear after changing the direction "inout" to "in" for "str_1" in entity "e2", but in my operative code I need bidirectional "str_1", and with this "inout" everything works fine for MAX10 and Cyclone_IV. And why did Quartus Prime put the GND driver in the "e2" entity, if it leads to an obvious drivers conflict? I hope that below code will help you find the cause and then create a fix. Here is the code with two entities: ###########################################################

[JDlug]

Something has cut the code, so here it is again: ########################################################### library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; entity e1 is port( data : out std_logic_vector(3 downto 0); clk : in std_logic ); end e1; architecture arch1 of e1 is component e2 is port( data : out std_logic_vector(3 downto 0); clk : in std_logic; str_1 : inout string(1 to 4); vec_1 : inout std_logic_vector(31 downto 0) ); end component; shared variable str_1 : string(1 to 4); shared variable vec_1 : std_logic_vector(31 downto 0); shared variable s1, s2 : std_logic; begin instance_1 : e2 PORT MAP ( data => data, clk => clk, str_1 => str_1, vec_1 => vec_1 ); process begin wait until clk'EVENT and clk='1'; s1 := not s2; end process; process begin wait until clk'EVENT and clk='1'; if s2/=s1 then s2:=s1; str_1:="ABCD"; end if; vec_1(7 downto 0):= conv_std_logic_vector(character'pos(str_1(1)),8); end process; end arch1; library IEEE; use IEEE.STD_LOGIC_1164.all; entity e2 is port( data : out std_logic_vector(3 downto 0); clk : in std_logic; str_1: inout string(1 to 4); vec_1: inout std_logic_vector(31 downto 0) ); end e2 ; architecture arch1 of e2 is begin process variable clk2: std_logic; begin wait until clk'EVENT and clk='1'; data<=vec_1(3 downto 0); clk2:= not clk2; end process; end arch1; ########################################################### Best Regards, (jd)

[JDlug]

Hi KhaiY, I attach the files you requested. Best Regards, (jd)

[KhaiChein_Y_Intel]

Hi JD,

Thanks for sharing the code. Could you share the QAR for Max/Cyclone (standard edition) and Stratix 10(Pro edition) as the QAR includes all the quartus settings in the design? If I open a new project and add the HDL file in the design, the quartus settings are not the same as your design.

Thanks.

Best regards,

KhaiY

[JDlug]

Hi KhaiY,

I attach the files you requested and which I already sent before by email but they haven't appeared here.

So I am doing it again directly from forum.

Best Regards,

(jd)

[KhaiChein_Y_Intel]

Hi JD,

Thanks for the QAR files. I can reproduced the same and I have sent the design file to engineering for investigation.

Thanks.

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi JD,

I received the update from the team, the fix is in the preliminary plan of the software in the future release. 

Thanks.

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi JD,

Do you have any questions or concerns before I transition this thread to community support?

Thanks.

Best regards,

KhaiY

[KhaiChein_Y_Intel]

Hi JD,

We do not receive any response from you to the previous reply/question that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Best regards,

KhaiY