In my design, there is a register that generates set/reset and control signals. From the clock status summary of the TimeQuest Timing Analyzer, it reports
Target Clock Type Status
inst39 Base Unconstrained.
Because inst39 does NOT generate a clock, it is not specified as a base clock or a generated clock. Following the Altera answer of my SR regarding this issue, I add the "-no_latch" option to the create_timing_netlist tcl command and remove " -model slow" option, the warning message about the unconstrained clock disappears. However, the hold check requirements for some other paths cann't no longer be met although the setup and hold checks are met for 3 models (slow 1200mV 85C, slow 1200mV 0C, and Fast 1200mV) from the comilation report of the Quartus-II. It is difficult for me to tell if my design meets the timing requirements. Please advise. Many thanks.
