Problem in VHDL

[Altera_Forum]

I'm trying to use variables in a LOOP to initialize all elements of a matrix, but i have a small problem. 

 Warning (10027): Verilog HDL or VHDL warning at the main.vhd(398): index expression is not wide enough to address all of the elements in the array   can anyone help me plz?

[Altera_Forum]

Could you post your code? It's difficult to guess otherwise. It could be a discrepancy between the number of loop iterations and the number of elements in your array. 

 That's just a guess though - it would be easier to say with the code.

[Altera_Forum]

PROCESS(do_rle) 

  variable inicializacao : INTEGER RANGE 0 TO 37;    variable temp_led_out : BIT := '0';    -- variaveis run length  variable rle_i : INTEGER RANGE 0 TO 7;  variable rle_j : INTEGER RANGE 0 TO 7;  variable rle_d : BIT;  variable count : INTEGER;  variable z : INTEGER RANGE 0 TO 63; -- contador do vetor final    variable walking_in_zero : BIT;    variable vetor_temp: vetor_de_int;       BEGIN   IF (do_rle'event AND do_rle = '1') THEN   rle_i := 0;  rle_j := 0;  rle_d := '1';  count := 0;  z := 1; -- contador do vetor final  walking_in_zero := '0';  vetor_temp(0) := tempMAT(0)(0);     FOR k IN 0 TO 62 LOOP        -- DECIDINDO O PROXIMO I e J ATRAVES DE ZIG ZAG  IF rle_i = 0 AND rle_d = '1' AND rle_j /=7 THEN    rle_j := rle_j + 1;  rle_d := '0';    ELSIF rle_j = 7 AND rle_i /=0 AND rle_d = '1' THEN    rle_i := rle_i + 1;  rle_d := '0';      ELSIF rle_j = 0 AND rle_d = '0' AND rle_i /= 7 THEN    rle_i := rle_i + 1;  rle_d := '1';    ELSIF rle_i = 7 AND rle_d = '0' THEN    rle_j := rle_j + 1;  rle_d := '1';    ELSIF rle_d = '1' THEN    rle_j := rle_j + 1;  rle_i := rle_i - 1;    ELSE    rle_j := rle_j - 1;  rle_i := rle_i + 1;    END IF;    IF (vetor_temp(k) = "0000000000000000") THEN  count := count + 1;  ELSIF ( count /= 0 ) THEN  vetor_temp(z) := "0000000000000000";  vetor_temp(z+1) := CONV_STD_LOGIC_VECTOR(count,16);  vetor_temp(z+2) := tempMAT(rle_i)(rle_j);  z := z + 3;  count := 0;  ELSE   vetor_temp(z) := tempMAT(rle_i)(rle_j);  z := z+1;  END IF;    IF rle_i = 7 AND rle_j = 7 THEN  vetor_temp(z) := tempMAT(rle_i)(rle_j);  vetor_temp(z+1) := count;  z := z+1;  EXIT;  END IF;  END LOOP;

[Altera_Forum]

How is "vetor_de_int" defined? 

 Which line is 398 of main.vhd?

[Altera_Forum]

Loops in VHDL are not like loops in C. a loop inside a process is going to create lots of parallel or in your case a large amount of unregistered logic. 

 I also notice you dont appear have any output from the process in the way of a signal or a port. I think you need to go away and read up about digital design. VHDL cannot be written like software.

[Altera_Forum]

TYPE vetor_de_int IS ARRAY(0 TO 63) OF STD_LOGIC_VECTOR ( 0 TO 15 ); 

shared variable vetor: vetor_de_int;

[Altera_Forum]

This code is NEVER going to synthesize into anything meaningful, because you are using variables and shared variables all other the place. It may work in simulation, but Im 99% sure you wont get it work on an FPGA in its current state. 

 You have to use SIGNALs to do what you're trying to do. And your code says you do not understand digital design. It looks like youre trying to write programming code.

[Altera_Forum]

I basically share tricky's doubts. In particular I don't see anything initialized in the code. I can't imagine to have ever seen the said warning. It seems to be issued by Quartus at a rather high level of code strangeness.

[Altera_Forum]

I would concur with FvM and tricky here. 

 If you're new to FPGA design and the VHDL language then basically use signals and forget about variables. You won't have to use variables at all. When you've done a bit of coding then you might start to see how regular (not shared) variables might come in useful. I've only ever used shared variables for very high levvel testbench code - forget about it for the FPGA code.  Basically you're designing digital logic. Your VHDL code is a description of that digital logic so your code should resemble the circuit: counters, adders, multiplexers etc. Sketch out what you want to produce on paper first in terms of these components. Your code should then have a direct correlation to this.  Ask yourself what bit of logic would your shared variable look like. At best it would be either: some lump of logic with lots of inputs directly driving it with no priority or a huge lump of prioritisation logic; or a load of identical lumps of logic with their outputs driving each other. I would be very very surprised if Quartus actually lets you use shard variables for synthesis - but seriously you don't need them.  Don't think of VHDL as another programming language. It isn't - it's a hardware description language. Don't think, this is how I do it in C/Java/anything else, how will VHDL let me do that. Think about logic and circuits and sketch it on paper first.  Hope this helps