Issues with Partial reconfiguration.

[DeusMMJr]

Hi, i'm facing with issues relative to blinking_led partial reconfiguration example .sof recording. When i'm trying to program .rfb file, Programmer reports a error relative to access TIMEOUT and also, reports that PR_ERROR flag goes to high, signal from Partial reconfiguration controller IP, i think.

Someone already faced with the same issue? Dip switches positions should stay in default configuration?

I'm using the Arria 10 GX Development kit.

[JohnT_Intel]

Hi,

Are you using internal host or external host? How do you send your data to the PR IP?​

[DeusMMJr]

Internal host Deusdete Miranda Matos Junior Processamento de Alto Desempenho SENAI/CIMATEC Sistema FIEB | www.fieb.org.br (71) 3462-8404 deusdete.junior@fieb.org.br

[DeusMMJr]

I did try send by USB Blaster. I'm using internal host. Deusdete Miranda Matos Junior Processamento de Alto Desempenho SENAI/CIMATEC Sistema FIEB | www.fieb.org.br (71) 3462-8404 deusdete.junior@fieb.org.br

[JohnT_Intel]

Hi,

May I know how do you implement your design using internal host? Is your data is being sent to the PR IP correct?

You can refer to https://fpgawiki.intel.com/wiki/Partial_Reconfiguration_Example_Design_with_Avalon_MM as your example​

[DeusMMJr]

I tried to follow the document published in https://www.intel.com/content/www/us/en/programmable/documentation/ihj1482170009390.html I have a special doubt about this tutorial. When, exactly, should I export root_partition_static.qdb? Thanks a lot JohnT (Intel) Hi, May I know how do you implement your design using internal host? Is your data is being sent to the PR IP correct? You can refer to https://fpgawiki.intel.com/ AN 797: Partially Reconfiguring a Design on Intel Arria 10 ...<https://www.intel.com/content/www/us/en/programmable/documentation/ihj1482170009390.html> www.intel.com Partial reconfiguration (PR) feature allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. You can create multiple personas for a particular region in your design, without impacting operation in areas outside this region. This methodology ... Deusdete Miranda Matos Junior Processamento de Alto Desempenho SENAI/CIMATEC Sistema FIEB | www.fieb.org.br<http://www.fieb.org.br> (71) 3462-8404 deusdete.junior@fieb.org.br

[DeusMMJr]

I'm trying to use USB-blaster to program .sof and .rfb, am I wrong? How can I use PCIe to send bitstream? The example that you sent is about Stratix V, I will try portability for Arria 10. Deusdete Miranda Matos Junior Processamento de Alto Desempenho SENAI/CIMATEC Sistema FIEB | www.fieb.org.br<http://www.fieb.org.br> (71) 3462-8404 deusdete.junior@fieb.org.br

[DeusMMJr]

Hi Jhon, I had success changing the USB-blaster frequency from 24MHz to 6MHz. But, I want to test PR programming with PCIe. Have you some example ou tips? Deusdete Miranda Matos Junior Processamento de Alto Desempenho SENAI/CIMATEC Sistema FIEB | www.fieb.org.br<http://www.fieb.org.br> (71) 3462-8404 deusdete.junior@fieb.org.br

[JohnT_Intel]

The design is similar to the JTAG Master. You just need to change the connection for the design from JTAG Master to PCIe. Then you can directly control the PR IP through PCIe. You may follow the System Console TCL on how to send the data to the PR IP by converting the code to PCIe driver.​